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Deduce processor type in define_code_functions.py
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tmr232 committed Jun 23, 2017
1 parent da80188 commit d147ff3
Showing 1 changed file with 29 additions and 15 deletions.
44 changes: 29 additions & 15 deletions define_code_functions.py
Original file line number Diff line number Diff line change
Expand Up @@ -25,31 +25,45 @@
#
##############################################################################################
import re
import idaapi

################### USER DEFINED VALUES ###################
# Enter a regular expression for how this architecture usually begins and ends functions.
# If the architecture does not dictate how to start or end a function use r".*" to allow
# for any instruction

# 8051 Architecture Prologue and Epilogue
smart_prolog = re.compile(r".*")
smart_epilog = re.compile(r"reti{0,1}")
processor_name = idaapi.get_inf_structure().procName

# PIC18 Architecture Prologue and Epilogue
#smart_prolog = re.compile(r".*")
#smart_epilog = re.compile(r"return 0")

# Mitsubishi M32R Architecutre Prologue and Epilogue
#smart_prolog = re.compile(r"push +lr")
#smart_epilog = re.compile(r"jmp +lr.*")
if processor_name == '8051':
# 8051 Architecture Prologue and Epilogue
smart_prolog = re.compile(r".*")
smart_epilog = re.compile(r"reti{0,1}")

elif processor_name == 'PIC18Cxx':
# PIC18 Architecture Prologue and Epilogue
smart_prolog = re.compile(r".*")
smart_epilog = re.compile(r"return 0")

elif processor_name == 'm32r':
# Mitsubishi M32R Architecutre Prologue and Epilogue
smart_prolog = re.compile(r"push +lr")
smart_epilog = re.compile(r"jmp +lr.*")

elif processor_name == 'TMS32028':
# Texas Instruments TMS320C28x
smart_prolog = re.compile(r".*")
smart_epilog = re.compile(r"lretr")

elif processor_name == 'AVR':
# AVR
smart_prolog = re.compile(r"push +r")
smart_epilog = re.compile(r"reti{0,1}")

else:
raise NotImplementedError('Unsupported processor type.')

# Texas Instruments TMS320C28x
#smart_prolog = re.compile(r".*")
#smart_epilog = re.compile(r"lretr")

# AVR
#smart_prolog = re.compile(r"push +r")
#smart_epilog = re.compile(r"reti{0,1}")
############################################################

start_addr = AskAddr(MinEA(), "Please enter the starting address for the data to be defined.")
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