Pointer typed

.gitignore

@@ -54,3 +54,4 @@ autoconf/autom4te.cache
 .vs
 # clangd index
 .clangd
+.history/

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h

@@ -376,6 +376,7 @@ enum {
 
   /// Keeping track of the number of the GI opcodes. Must be the last entry.
   GIU_NumOpcodes,
+  GIM_CheckvtAny32,
 };
 
 enum {

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

@@ -175,7 +175,7 @@ bool InstructionSelector::executeMatchTable(
       CurrentIdx = MatchTable[CurrentIdx + (Opcode - LowerBound)];
       if (!CurrentIdx) {
         CurrentIdx = Default;
-	break;
+	      break;
       }
       OnFailResumeAt.push_back(Default);
       break;
@@ -396,7 +396,8 @@ bool InstructionSelector::executeMatchTable(
         unsigned AddrSpace = MatchTable[CurrentIdx++];
         DEBUG_WITH_TYPE(
           TgtInstructionSelector::getName(),
-          dbgs() << "addrspace(" << MMOAddrSpace << ") vs "
+          dbgs() << CurrentIdx << ": GIM_CheckMemoryAddressSpace " 
+                 << "addrspace(" << MMOAddrSpace << ") vs "
                  << AddrSpace << '\n');
 
         if (AddrSpace == MMOAddrSpace) {
@@ -532,6 +533,32 @@ bool InstructionSelector::executeMatchTable(
       }
       break;
     }
+    case GIM_CheckvtAny32: {
+      dbgs() << "YOOOOOOOO\n";
+      int64_t InsnID = MatchTable[CurrentIdx++];
+      int64_t OpIdx = MatchTable[CurrentIdx++];
+      int64_t SizeInBits = MatchTable[CurrentIdx++];
+
+      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+                      dbgs() << CurrentIdx << ": GIM_CheckvtAny32MIs["
+                             << InsnID << "]->getOperand(" << OpIdx
+                             << "), SizeInBits=" << SizeInBits << ")\n");
+      assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
+      MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
+      const LLT Ty = MRI.getType(MO.getReg());
+      dbgs() << "Ty size " << Ty.getSizeInBits() << "\n";
+      dbgs() << "SizeInBits" << SizeInBits << "\n";
+
+      if (Ty.getSizeInBits() != SizeInBits) {
+        if (handleReject() == RejectAndGiveUp)
+          return false;
+      } 
+      /*else if (handleReject() == RejectAndGiveUp)
+        return false;*/
+
+      break;
+    }
+
     case GIM_CheckPointerToAny: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
@@ -770,6 +797,9 @@ bool InstructionSelector::executeMatchTable(
       if (NewInsnID >= OutMIs.size())
         OutMIs.resize(NewInsnID + 1);
 
+      auto T = State.MIs[0];
+      dbgs() << "Dumping MI in GIR_BuildMI";
+      T->dump();
       OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0],
                                   State.MIs[0]->getDebugLoc(), TII.get(Opcode));
       DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),

llvm/include/llvm/CodeGen/ValueTypes.td

@@ -166,6 +166,9 @@ def FlagVT : ValueType<0  , 131>;   // Pre-RA sched glue
 def isVoid : ValueType<0  , 132>;   // Produces no value
 def untyped: ValueType<8  , 133>;   // Produces an untyped value
 def exnref: ValueType<0, 134>;      // WebAssembly's exnref type
+
+def vtAny32: ValueType<32, 247>;   // Match any 32-bit type.
+
 def token  : ValueType<0  , 248>;   // TokenTy
 def MetadataVT: ValueType<0, 249>;  // Metadata
 

llvm/include/llvm/Support/MachineValueType.h

@@ -227,6 +227,9 @@ namespace llvm {
       // This value must be a multiple of 32.
       MAX_ALLOWED_VALUETYPE = 160,
 
+      // Match any 32-bit type. 
+      vtAny32        = 247,
+
       // A value of type llvm::TokenTy
       token          = 248,
 
@@ -306,6 +309,10 @@ namespace llvm {
               SimpleTy <= MVT::LAST_INTEGER_VALUETYPE);
     }
 
+    bool isvtAny32() const {
+      return (SimpleTy == MVT::vtAny32);
+    }
+
     /// Return true if this is a vector value type.
     bool isVector() const {
       return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
@@ -695,6 +702,7 @@ namespace llvm {
                          "in codegen and has no size");
       case Metadata:
         llvm_unreachable("Value type is metadata.");
+      case vtAny32: return TypeSize::Fixed(32);
       case i1:
       case v1i1: return TypeSize::Fixed(1);
       case nxv1i1: return TypeSize::Scalable(1);

llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

@@ -154,8 +154,13 @@ def : GINodeEquiv<G_LOAD, atomic_load> {
   let CheckMMOIsNonAtomic = 0;
   let CheckMMOIsAtomic = 1;
 }
-
 def : GINodeEquiv<G_ATOMIC_CMPXCHG, atomic_cmp_swap>;
+
+def : GINodeEquiv<G_LOAD, new_atomic_load> {
+  let CheckMMOIsNonAtomic = 0;
+  let CheckMMOIsAtomic = 1;
+}
+
 def : GINodeEquiv<G_ATOMICRMW_XCHG, atomic_swap>;
 def : GINodeEquiv<G_ATOMICRMW_ADD, atomic_load_add>;
 def : GINodeEquiv<G_ATOMICRMW_SUB, atomic_load_sub>;

llvm/include/llvm/Target/TargetSelectionDAG.td

@@ -282,6 +282,11 @@ def SDTAtomicLoad : SDTypeProfile<1, 1, [
   SDTCisInt<0>, SDTCisPtrTy<1>
 ]>;
 
+// TODO: Put restriction on 0th operand too.
+def SDTNewAtomicLoad : SDTypeProfile<1, 1, [
+  SDTCisPtrTy<1>
+]>;
+
 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
   SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
 ]>;
@@ -615,6 +620,9 @@ def atomic_load_fsub : SDNode<"ISD::ATOMIC_LOAD_FSUB" , SDTFPAtomic2,
 
 def atomic_load      : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
                     [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+def new_atomic_load  : SDNode<"ISD::ATOMIC_LOAD", SDTNewAtomicLoad,
+                    [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+
 def atomic_store     : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
                     [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
@@ -1565,6 +1573,21 @@ def atomic_load_32 :
   let IsAtomic = 1;
   let MemoryVT = i32;
 }
+
+def atomic_load_iptr :
+  PatFrag<(ops node:$ptr),
+          (new_atomic_load node:$ptr)> {
+  let IsAtomic = 1;
+  let MemoryVT = i32;
+}
+
+def atomic_load_vtany32 :
+  PatFrag<(ops node:$ptr),
+          (new_atomic_load node:$ptr)> {
+  let IsAtomic = 1;
+  let MemoryVT = vtAny32;
+}
+
 def atomic_load_64 :
   PatFrag<(ops node:$ptr),
           (atomic_load node:$ptr)> {

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -1,3 +1,4 @@
+;
 //===- SelectionDAGISel.cpp - Implement the SelectionDAGISel class --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
@@ -2529,6 +2530,7 @@ CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
                    const SelectionDAGISel &SDISel, SDNode *N) {
+  //dbgs() << "passing to check pred " << (unsigned) MatcherTable[MatcherIndex] << "\n"; 
   return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
 }
 
@@ -2540,14 +2542,28 @@ CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
   return N->getOpcode() == Opc;
 }
 
+/*
+LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
+isvtAny32Compatible (MVT::SimpleValueType T) {
+  return T == MVT::i32 || T == MVT::f32;
+}
+*/
+
 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
           const TargetLowering *TLI, const DataLayout &DL) {
+  dbgs() << "In check type\n";
   MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
   if (N.getValueType() == VT) return true;
 
+  if (VT == MVT::vtAny32) { //dbgs() << "Matching *****\n"; return isvtAny32Compatible(N.getValueType()); 
+    dbgs() << "Matching ***\n";
+    return true;
+  }
+
   // Handle the case when VT is iPTR.
   return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL);
+
 }
 
 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
@@ -2659,9 +2675,10 @@ static unsigned IsPredicateKnownToFail(const unsigned char *Table,
   case SelectionDAGISel::OPC_CheckPatternPredicate:
     Result = !::CheckPatternPredicate(Table, Index, SDISel);
     return Index;
-  case SelectionDAGISel::OPC_CheckPredicate:
+  case SelectionDAGISel::OPC_CheckPredicate: {
     Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
     return Index;
+  }
   case SelectionDAGISel::OPC_CheckOpcode:
     Result = !::CheckOpcode(Table, Index, N.getNode());
     return Index;
@@ -3056,6 +3073,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
       if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
       continue;
     case OPC_CheckPredicate:
+      dbgs() << "Check pred\n";
       if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
                                 N.getNode()))
         break;
@@ -3407,6 +3425,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
     case OPC_EmitNode:     case OPC_MorphNodeTo:
     case OPC_EmitNode0:    case OPC_EmitNode1:    case OPC_EmitNode2:
     case OPC_MorphNodeTo0: case OPC_MorphNodeTo1: case OPC_MorphNodeTo2: {
+      dbgs() << "Enter in interpreter\n";
       uint16_t TargetOpc = MatcherTable[MatcherIndex++];
       TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
       unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
@@ -3426,6 +3445,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
           (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
         if (VT == MVT::iPTR)
           VT = TLI->getPointerTy(CurDAG->getDataLayout()).SimpleTy;
+        if (VT == MVT::vtAny32)
+          VT = MVT::i32;
         VTs.push_back(VT);
       }
 

llvm/lib/CodeGen/ValueTypes.cpp

@@ -155,6 +155,7 @@ std::string EVT::getEVTString() const {
   case MVT::Metadata:return "Metadata";
   case MVT::Untyped: return "Untyped";
   case MVT::exnref : return "exnref";
+  case MVT::vtAny32 : return "vtAny32";
   }
 }
 

llvm/lib/Target/AMDGPU/AMDGPUGISel.td

@@ -133,6 +133,9 @@ def : GINodeEquiv<G_LOAD, AMDGPUatomic_ld_glue> {
   bit CheckMMOIsAtomic = 1;
 }
 
+def : GINodeEquiv<G_LOAD, AMDGPUatomic_new_ld_glue> {
+  bit CheckMMOIsAtomic = 1;
+}
 
 
 def : GINodeEquiv<G_ATOMIC_CMPXCHG, atomic_cmp_swap_glue>;

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

@@ -2096,6 +2096,9 @@ void AMDGPUInstructionSelector::initM0(MachineInstr &I) const {
 
 bool AMDGPUInstructionSelector::selectG_LOAD_ATOMICRMW(MachineInstr &I) const {
   initM0(I);
+  if (I.getOpcode() == 62) 
+    dbgs() << "begin atomic load\n";
+
   return selectImpl(I, *CoverageInfo);
 }
 

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

@@ -407,6 +407,16 @@ def atomic_load_32_#as : PatFrag<(ops node:$ptr), (atomic_load_32 node:$ptr)> {
   let MemoryVT = i32;
 }
 
+def atomic_load_iptr_#as : PatFrag<(ops node:$ptr), (atomic_load_iptr node:$ptr)> {
+  let IsAtomic = 1;
+  let MemoryVT = i32;
+}
+
+def atomic_load_vtany32_#as : PatFrag<(ops node:$ptr), (atomic_load_vtany32 node:$ptr)> {
+  let IsAtomic = 1;
+  let MemoryVT = vtAny32;
+}
+
 def atomic_load_64_#as : PatFrag<(ops node:$ptr), (atomic_load_64 node:$ptr)> {
   let IsAtomic = 1;
   let MemoryVT = i64;

llvm/lib/Target/AMDGPU/DSInstructions.td

@@ -245,6 +245,14 @@ multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOu
   }
 }
 
+multiclass DS_1A_RET_mc_new<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
+  def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
+
+  let has_m0_read = 0 in {
+    def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
+  }
+}
+
 class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
   DS_1A_RET<opName, rc, 1>;
 
@@ -539,7 +547,7 @@ defm DS_READ_I8      : DS_1A_RET_mc<"ds_read_i8">;
 defm DS_READ_U8      : DS_1A_RET_mc<"ds_read_u8">;
 defm DS_READ_I16     : DS_1A_RET_mc<"ds_read_i16">;
 defm DS_READ_U16     : DS_1A_RET_mc<"ds_read_u16">;
-defm DS_READ_B32     : DS_1A_RET_mc<"ds_read_b32">;
+defm DS_READ_B32     : DS_1A_RET_mc_new<"ds_read_b32">;
 defm DS_READ_B64     : DS_1A_RET_mc<"ds_read_b64", VReg_64>;
 
 defm DS_READ2_B32    : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>;
@@ -622,8 +630,9 @@ def : GCNPat <
   (DS_SWIZZLE_B32 VGPR_32:$src, (as_i16timm $offset16), (i1 0))
 >;
 
-class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
-  (vt (frag (DS1Addr1Offset i32:$ptr, i16:$offset))),
+// frag is acting as predicate.
+class DSReadPat <DS_Pseudo inst, ValueType vt1, PatFrag frag, int gds=0> : GCNPat <
+  (vt1 (frag (DS1Addr1Offset i32:$ptr, i16:$offset))),
   (inst $ptr, offset:$offset, (i1 gds))
 >;
 
@@ -656,10 +665,16 @@ defm : DSReadPat_mc <DS_READ_U16, i32, "zextloadi16_local">;
 defm : DSReadPat_mc <DS_READ_U16, i16, "load_local">;
 
 foreach vt = Reg32Types.types in {
-defm : DSReadPat_mc <DS_READ_B32, vt, "load_local">;
+//defm : DSReadPat_mc <DS_READ_B32, vt, "load_local">;
 }
 
-defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
+//defm : DSReadPat_mc <DS_READ_B32, p3,  "atomic_load_iptr_local">;
+defm : DSReadPat_mc <DS_READ_B32, vtAny32,  "atomic_load_vtany32_local">;
+//defm : DSReadPat_mc <DS_READ_B32, vtAny32,  "atomic_load_iptr_local">;
+//defm : DSReadPat_mc <DS_READ_B32, vtAny32,  "atomic_load_vtany32_local">;
+//defm : DSReadPat_mc <DS_READ_B32, vtAny32,  "atomic_load_vtany32_local">;
+
+//defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
 defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
 
 let AddedComplexity = 100 in {