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1. ssp ssp Public

   Statistical Digital Signal Processing and Modeling

   Python 4

2. dsp dsp Public

   Statistical Digital Signal Processing Algorithms

   Jupyter Notebook

3. cpu-mips cpu-mips Public

   MIPS processor with a 5-stage pipeline

   Verilog

4. molfat_rtl_kirschEdgeDetecter molfat_rtl_kirschEdgeDetecter Public

   Synthesizable Kirsch Edge Detector for 90nm CMOS; 4-stage fully pipelined design; 205MHz (4.9ns);

   VHDL

5. eagleCAD eagleCAD Public

   All things EAGLE CAD

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