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IMDS2/IPB/IPC fixes #13419

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IMDS2/IPB/IPC fixes #13419

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1d934a5
ipc: Correct ROM map of Intel IPC
Googulator Feb 25, 2025
d38920d
ipc: Implement differences between IPB and IPC
Googulator Feb 25, 2025
82bb5bc
ipc: Correct ROM sets for IPB
Googulator Feb 25, 2025
fb9f0dd
ipc: Implement bootstrap ROM en/disable, fix wrong end address
Googulator Feb 25, 2025
dc37e21
ipc: fix missing declarations and initializations
Googulator Feb 26, 2025
c2865e1
Add 23.4MHz crystal found on Intel IPB
Googulator Feb 26, 2025
ea1452c
ipc: Fix boundary and initial state of m_boot
Googulator Feb 26, 2025
3691d09
ipc: add alternate v1.2 ROM set found in an actual IPB
Googulator Feb 27, 2025
11d9946
ipc: correct clock frequency for IPC
Googulator Feb 27, 2025
689af6e
imds2: Document exactly which MDS model is emulated
Googulator Feb 27, 2025
88c40c8
ipc: unmapped memory addresses and IO ports return 0, not 0xFF
Googulator Feb 28, 2025
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1 change: 1 addition & 0 deletions src/emu/xtal.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -359,6 +359,7 @@ const double XTAL::known_xtals[] = {
22'680'000, // 22.680_MHz_XTAL HDS200 80-columns display clock
22'896'000, // 22.896_MHz_XTAL DEC VT220 132-column display clock
23'200'000, // 23.2_MHz_XTAL Roland JV-80 & JV-880 PCM clock
23'400'000, // 23.4_MHz_XTAL Intel Integrated Processor Board (IPB) from iMDS2
23'814'000, // 23.814_MHz_XTAL TeleVideo TVI-912, 920 & 950
23'961'600, // 23.9616_MHz_XTAL Osborne 4 (Vixen)
24'000'000, // 24_MHz_XTAL Mario, 80's Data East games, 80's Konami games
Expand Down
8 changes: 5 additions & 3 deletions src/mame/intel/imds2.cpp
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Expand Up @@ -2,7 +2,7 @@
// copyright-holders:F. Ulivi
//
// ***************************************
// Driver for Intel Intellec MDS series-II
// Driver for Intel Intellec Series II MDS
// ***************************************
//
// Documentation used for this driver:
Expand All @@ -13,7 +13,9 @@
//
// All these manuals are available on http://www.bitsavers.org
//
// An Intellec MDS series-II is composed of the following boards:
// The default configuration emulated by this driver is equivalent to a Model 225 MDS.
//
// An Intellec Series II MDS is composed of the following boards:
//
// **********
// Integrated Processor Card (IPC) or Integrated Processor Board (IPB)
Expand Down Expand Up @@ -347,4 +349,4 @@ ROM_END


/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME */
COMP( 1979, imds2, 0, 0, imds2, imds2, imds2_state, empty_init, "Intel", "Intellec MDS-II", 0)
COMP( 1979, imds2, 0, 0, imds2, imds2, imds2_state, empty_init, "Intel", "Intellec Series II Microcomputer Development System, Model 225", 0)
135 changes: 116 additions & 19 deletions src/mame/intel/ipc.cpp
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Expand Up @@ -27,20 +27,23 @@


Preliminary Memory Map
E800-F7FF BIOS ROM area
0000-7FFF Onboard RAM (IPB & IPC)
8000-F7FF Onboard RAM (IPC only)
E800-EFFF Bootstrap & diagnostic ROM
F800-FFFF Monitor ROM (or other user interface)

I/O F4/F5 main console input and output
I/O F6/F7 alternate console input
I/O FF ROM control (enable/disable access to bootstrap ROM)

ToDo:
- Everything!
- iPC - Find missing rom F800-FFFF

****************************************************************************/

#include "emu.h"
#include "cpu/i8085/i8085.h"
#include "machine/74259.h"
#include "machine/i8251.h"
#include "machine/pit8253.h"
#include "bus/rs232/rs232.h"
Expand All @@ -54,33 +57,73 @@ class ipc_state : public driver_device
ipc_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
, m_ipcctrl(*this, "ipcctrl")
, m_boot(*this, "boot")
{ }

void ipc(machine_config &config);
void ipb(machine_config &config);

private:
void board_common(machine_config &config);
void io_map(address_map &map) ATTR_COLD;
void mem_map(address_map &map) ATTR_COLD;
void ipb_mem_map(address_map &map) ATTR_COLD;
void ipc_mem_map(address_map &map) ATTR_COLD;

virtual void machine_reset() override ATTR_COLD;
virtual void driver_reset() override;
void ipc_control_w(uint8_t data);
required_device<cpu_device> m_maincpu;
required_device<ls259_device> m_ipcctrl;
memory_view m_boot;
};


void ipc_state::mem_map(address_map &map)
void ipc_state::ipb_mem_map(address_map &map)
{
map.unmap_value_high();
map(0x0000, 0xdfff).ram();
map(0xe800, 0xffff).rom().region("roms", 0);
map.unmap_value_low();
map(0x0000, 0x7fff).ram();

// selectively map the boot/diagnostic segment
map(0x0000, 0xefff).view(m_boot);

// SEL_BOOT/ == 0 and START_UP/ == 0
m_boot[0](0x0000, 0x07ff).rom().region("roms", 0);
m_boot[0](0xe800, 0xefff).rom().region("roms", 0);

// SEL_BOOT/ == 0 and START_UP/ == 1
m_boot[1](0xe800, 0xefff).rom().region("roms", 0);

map(0xf800, 0xffff).rom().region("roms", 0x800);
}


void ipc_state::ipc_mem_map(address_map &map)
{
map.unmap_value_low();
map(0x0000, 0xffff).ram();

// selectively map the boot/diagnostic segment
map(0x0000, 0xefff).view(m_boot);

// SEL_BOOT/ == 0 and START_UP/ == 0
m_boot[0](0x0000, 0x07ff).rom().region("roms", 0);
m_boot[0](0xe800, 0xefff).rom().region("roms", 0);

// SEL_BOOT/ == 0 and START_UP/ == 1
m_boot[1](0xe800, 0xefff).rom().region("roms", 0);

map(0xf800, 0xffff).rom().region("roms", 0x800);
}

void ipc_state::io_map(address_map &map)
{
map.unmap_value_high();
map.unmap_value_low();
map.global_mask(0xff);
map(0xf0, 0xf3).rw("pit", FUNC(pit8253_device::read), FUNC(pit8253_device::write));
map(0xf4, 0xf5).rw("uart1", FUNC(i8251_device::read), FUNC(i8251_device::write));
map(0xf6, 0xf7).rw("uart2", FUNC(i8251_device::read), FUNC(i8251_device::write));
map(0xff, 0xff).w(FUNC(ipc_state::ipc_control_w));
}

/* Input ports */
Expand All @@ -93,14 +136,48 @@ void ipc_state::machine_reset()
m_maincpu->set_state_int(i8085a_cpu_device::I8085_PC, 0xE800);
}

void ipc_state::driver_reset()
{
m_boot.select(0);
}

void ipc_state::ipc_control_w(uint8_t data)
{
// b3 is ~(bit to be written)
// b2-b0 is ~(no. of bit to be written)
m_ipcctrl->write_bit(~data & 7, BIT(~data, 3));

// SEL_BOOT/ == 0
if (!m_ipcctrl->q3_r())
// START_UP/
m_boot.select(m_ipcctrl->q5_r());
else
m_boot.disable();
}


void ipc_state::ipc(machine_config &config)
{
/* basic machine hardware */
I8085A(config, m_maincpu, XTAL(19'660'800) / 4);
m_maincpu->set_addrmap(AS_PROGRAM, &ipc_state::mem_map);
I8085A(config, m_maincpu, XTAL(8'000'000));
m_maincpu->set_addrmap(AS_PROGRAM, &ipc_state::ipc_mem_map);
m_maincpu->set_addrmap(AS_IO, &ipc_state::io_map);
board_common(config);
}


void ipc_state::ipb(machine_config &config)
{
/* basic machine hardware */
I8080A(config, m_maincpu, XTAL(23'400'000) / 9);
m_maincpu->set_addrmap(AS_PROGRAM, &ipc_state::ipb_mem_map);
m_maincpu->set_addrmap(AS_IO, &ipc_state::io_map);
board_common(config);
}


void ipc_state::board_common(machine_config &config)
{
pit8253_device &pit(PIT8253(config, "pit", 0));
pit.set_clk<0>(XTAL(19'660'800) / 16);
pit.set_clk<1>(XTAL(19'660'800) / 16);
Expand All @@ -110,7 +187,7 @@ void ipc_state::ipc(machine_config &config)
pit.out_handler<1>().set("uart2", FUNC(i8251_device::write_txc));
pit.out_handler<1>().append("uart2", FUNC(i8251_device::write_rxc));

i8251_device &uart1(I8251(config, "uart1", 0)); // 8 data bits, no parity, 1 stop bit, 9600 baud
i8251_device &uart1(I8251(config, "uart1", 0)); // 8 data bits, no parity, 2 stop bits, 110 baud
uart1.txd_handler().set("rs232a", FUNC(rs232_port_device::write_txd));
uart1.dtr_handler().set("rs232a", FUNC(rs232_port_device::write_dtr));
uart1.rts_handler().set("rs232a", FUNC(rs232_port_device::write_rts));
Expand All @@ -129,26 +206,46 @@ void ipc_state::ipc(machine_config &config)
rs232b.rxd_handler().set("uart2", FUNC(i8251_device::write_rxd));
rs232b.dsr_handler().set("uart2", FUNC(i8251_device::write_dsr));
rs232b.cts_handler().set("uart2", FUNC(i8251_device::write_cts));

LS259(config, m_ipcctrl);
}

/* ROM definition */
ROM_START( ipb )
ROM_REGION( 0x1800, "roms", 0 )
ROM_LOAD( "ipb_e8_v1.3.bin", 0x0000, 0x0800, CRC(fc9d4703) SHA1(2ce078e1bcd8b24217830c54bcf04c5d146d1b76) )
ROM_LOAD( "ipb_f8_v1.3.bin", 0x1000, 0x0800, CRC(966ba421) SHA1(d6a904c7d992a05ed0f451d7d34c1fc8de9547ee) )
ROM_REGION( 0x1000, "roms", 0 )
ROM_DEFAULT_BIOS("mon12")
// 1x2732 Copyright 1979 (in IPC)
// note: it's not clear if an IPB ever shipped with this ROM, but aftermarket ROM upgrades to 1.3 were common
ROM_SYSTEM_BIOS(0, "mon13", "Series II Monitor v1.3")
ROMX_LOAD( "ipc_v1.3_104584-001.u82", 0x0000, 0x1000, CRC(0889394f) SHA1(b7525baf1884a7d67402dea4b5566016a9861ef2), ROM_BIOS(0) )
// 2x2716 Copyright 1978
ROM_SYSTEM_BIOS(1, "mon12", "Series II Monitor v1.2")
ROMX_LOAD( "ipb_e8_v1.2.bin", 0x0000, 0x0800, CRC(6496efaf) SHA1(1a9c0f1b19c1807803db3f1543f51349d7fd693a), ROM_BIOS(1) )
ROMX_LOAD( "ipb_f8_v1.2.bin", 0x0800, 0x0800, CRC(258dc9a6) SHA1(3fde993aee06d9af5093d7a2d9a8cbd71fed0951), ROM_BIOS(1) )
// 2x2716 Copyright 1978 (overwritten in F8 ROM by new code)
// this version was discovered in an IPB with Siemens branding, saved from e-waste - it's unofficial, but is definitely out there
// it's an adaptation to work with a 600 baud teleprinter with slow carriage return
// the names are derived from the chips' markings ("BOOT 600Bd" and "MON 2 600Bd")
// note: expect checksum messages from this ROM set, as whoever made it never bothered to correct the checksums
ROM_SYSTEM_BIOS(2, "mon12_600bd", "Series II Monitor v1.2 - 600 baud teleprinter version")
ROMX_LOAD( "ipb_e8_v1.2_boot_600bd.bin", 0x0000, 0x0800, CRC(6bf62535) SHA1(40ac2546c816884dffdaa0ed2c6e41eb8523dcd6), ROM_BIOS(2) )
ROMX_LOAD( "ipb_f8_v1.2_mon_2_600bd.bin", 0x0800, 0x0800, CRC(d5ace425) SHA1(d39cd3522ffd1d334f6eb128990e488ce07243ab), ROM_BIOS(2) )
// 2x2716 Copyright 1977
ROM_SYSTEM_BIOS(3, "mon11", "Series II Monitor v1.1")
ROMX_LOAD( "ipb_e8_v1.1.bin", 0x0000, 0x0800, CRC(ffb7c036) SHA1(6f60cdfe20621c4b633c972adcb644a1c02eaa39), ROM_BIOS(3) )
ROMX_LOAD( "ipb_e8_v1.1.bin", 0x0800, 0x0800, CRC(3696ff28) SHA1(38b435e10a81629430275aec051fb0a55ec1f6fd), ROM_BIOS(3) )
ROM_END

ROM_START( ipc )
ROM_REGION( 0x1800, "roms", ROMREGION_ERASEFF )
ROM_REGION( 0x1000, "roms", 0 )
ROM_LOAD( "ipc_v1.3_104584-001.u82", 0x0000, 0x1000, CRC(0889394f) SHA1(b7525baf1884a7d67402dea4b5566016a9861ef2) )
ROM_LOAD( "ipc_f8_v1.3.bin", 0x1000, 0x0800, NO_DUMP ) // rom name unknown
ROM_END

} // anonymous namespace


/* Driver */

/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP( 19??, ipb, 0, 0, ipc, ipc, ipc_state, empty_init, "Intel", "iPB", MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE )
COMP( 19??, ipc, ipb, 0, ipc, ipc, ipc_state, empty_init, "Intel", "iPC", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE )
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP( 1977, ipb, 0, 0, ipb, ipc, ipc_state, empty_init, "Intel", "Integrated Processor Board", MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE )
COMP( 1979, ipc, ipb, 0, ipc, ipc, ipc_state, empty_init, "Intel", "Integrated Processor Card", MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE )