The aim of this project is to compute the number of hits & misses if the list of hexadecimal addresses defined in "instructions.txt" is applied to caches with the following organisations:
(i) 128 byte 1-way cache with 16 bytes per line (direct mapped) (ii) 128 byte 2-way set associative cache with 16 bytes per line (iii) 128 byte 4-way set associative cache with 16 bytes per line (iv) 128 byte 8-way associative cache with 16 bytes per line (fully associative)