Add fuzzers for HCLK_CMT tiles.

Signed-off-by: Keith Rothman <[email protected]>

fuzzers/005-tilegrid/Makefile

@@ -15,6 +15,7 @@ TILEGRID_TDB_DEPENDENCIES += cfg_int/build/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += monitor_int/build/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += clk_hrow/build/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += clk_bufg/build/segbits_tilegrid.tdb
+TILEGRID_TDB_DEPENDENCIES += hclk_cmt/build/segbits_tilegrid.tdb
 GENERATE_FULL_ARGS=
 
 ifeq (${XRAY_DATABASE}, zynq7)
@@ -104,6 +105,9 @@ clk_hrow/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 clk_bufg/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 	cd clk_bufg && $(MAKE)
 
+hclk_cmt/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
+	cd hclk_cmt && $(MAKE)
+
 build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
 	python3 add_tdb.py \
 		--fn-in build/basicdb/tilegrid.json \
@@ -139,6 +143,7 @@ clean:
 	cd orphan_int_column && $(MAKE) clean
 	cd clk_hrow && $(MAKE) clean
 	cd clk_bufg && $(MAKE) clean
+	cd hclk_cmt && $(MAKE) clean
 
 .PHONY: database pushdb clean run
 

fuzzers/005-tilegrid/add_tdb.py

@@ -86,6 +86,7 @@ def run(fn_in, fn_out, verbose=False):
         ("dsp/build/segbits_tilegrid.tdb", 28, 10),
         ("clk_hrow/build/segbits_tilegrid.tdb", 30, 18),
         ("clk_bufg/build/segbits_tilegrid.tdb", 30, 8),
+        ("hclk_cmt/build/segbits_tilegrid.tdb", 30, 10),
         ("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words),
         ("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words),
         ("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words),

fuzzers/005-tilegrid/hclk_cmt/Makefile

@@ -0,0 +1,4 @@
+N ?= 5
+GENERATE_ARGS?="--oneval 1 --design params.csv --dword 5 --dframe 1C"
+include ../fuzzaddr/common.mk
+

fuzzers/005-tilegrid/hclk_cmt/generate.tcl

@@ -0,0 +1,3 @@
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+generate_top

fuzzers/005-tilegrid/hclk_cmt/top.py

@@ -0,0 +1,66 @@
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray.db import Database
+
+
+def gen_sites():
+    db = Database(util.get_db_root())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+        sites = []
+        for site, site_type in gridinfo.sites.items():
+            if site_type == 'BUFMRCE':
+                sites.append(site)
+
+        if sites:
+            yield tile_name, sorted(sites)
+
+
+def write_params(params):
+    pinstr = 'tile,val,site\n'
+    for tile, (site, val) in sorted(params.items()):
+        pinstr += '%s,%s,%s\n' % (tile, val, site)
+    open('params.csv', 'w').write(pinstr)
+
+
+def run():
+    print('''
+module top();
+    ''')
+
+    params = {}
+
+    sites = list(gen_sites())
+    for (tile_name, sites), isone in zip(sites,
+                                         util.gen_fuzz_states(len(sites))):
+        site_name = sites[0]
+        params[tile_name] = (site_name, isone)
+
+        print(
+            '''
+            wire clk_{site};
+            (* KEEP, DONT_TOUCH, LOC = "{site}" *)
+            BUFMRCE #(
+                .INIT_OUT({isone})
+                ) buf_{site} (
+                .O(clk_{site})
+            );
+
+            BUFR bufr_{site} (
+                .I(clk_{site})
+                );
+'''.format(
+                site=site_name,
+                isone=isone,
+            ))
+
+    print("endmodule")
+    write_params(params)
+
+
+if __name__ == '__main__':
+    run()

fuzzers/045-hclk-cmt-pips/Makefile

@@ -0,0 +1,65 @@
+export FUZDIR=$(shell pwd)
+PIP_TYPE?=hclk_cmt
+PIPLIST_TCL=$(FUZDIR)/hclk_cmt_pip_list.tcl
+TODO_RE=".*"
+# Skipped pips:
+# - LEAF wires are disconnected
+# - FREQ_REF is only used by interconnect clocks, so low likelyhood of usage.
+#   A BUFR can be used to clock divide if needed
+# - PHSR PIPs are connected to PHASER sites, which are undocumented, so avoid
+#   for now.
+EXCLUDE_RE="(^.*LEAF)|(HCLK_CMT_L\.[^.]+\.HCLK_CMT_MUX_CLK_[0-9]+)|(HCLK_CMT\.[^.]+\.HCLK_CMT_CK_IN[0-9]+)|(^.*BUFMR)|(^.*FREQ_REF)|(^.*PHSR)|(^.*CLK_PLL7)|(^.*CLK_MMCM13)"
+
+MAKETODO_FLAGS=--sides ",l" --pip-type ${PIP_TYPE} --seg-type ${PIP_TYPE} --re $(TODO_RE) --exclude-re $(EXCLUDE_RE)
+N = 50
+
+# These PIPs all appear to be either a 1 bit solutions.
+SEGMATCH_FLAGS=-c 2
+SPECIMENS_DEPS=build/cmt_regions.csv
+A_PIPLIST=hclk_cmt.txt
+
+include ../pip_loop.mk
+
+build/segbits_hclk_cmt.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_hclk_cmt.rdb \
+		$(shell find build -name segdata_hclk_cmt.txt)
+
+build/segbits_hclk_cmt_l.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_hclk_cmt_l.rdb \
+		$(shell find build -name segdata_hclk_cmt_l.txt)
+
+database: build/segbits_hclk_cmt.rdb build/segbits_hclk_cmt_l.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
+		--seg-fn-in build/segbits_hclk_cmt.rdb \
+		--seg-fn-out build/segbits_hclk_cmt.db
+
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
+		--seg-fn-in build/segbits_hclk_cmt_l.rdb \
+		--seg-fn-out build/segbits_hclk_cmt_l.db
+
+	# Keep a copy to track iter progress
+	cp build/segbits_hclk_cmt.rdb build/$(ITER)/segbits_hclk_cmt.rdb
+	cp build/segbits_hclk_cmt_l.rdb build/$(ITER)/segbits_hclk_cmt_l.rdb
+
+
+	${XRAY_MASKMERGE} build/mask_hclk_cmt.db \
+		$(shell find build -name segdata_hclk_cmt.txt)
+	${XRAY_MASKMERGE} build/mask_hclk_cmt_l.db \
+		$(shell find build -name segdata_hclk_cmt_l.txt)
+
+	# Clobber existing .db to eliminate potential conflicts
+	cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db build/database/${XRAY_DATABASE}
+	XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} hclk_cmt build/segbits_hclk_cmt.db
+	XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} hclk_cmt_l build/segbits_hclk_cmt_l.db
+
+build/cmt_regions.csv: output_cmt.tcl
+	mkdir -p build
+	cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl
+
+pushdb: database
+	${XRAY_MERGEDB} hclk_cmt build/segbits_hclk_cmt.db
+	${XRAY_MERGEDB} hclk_cmt_l build/segbits_hclk_cmt_l.db
+	${XRAY_MERGEDB} mask_hclk_cmt build/mask_hclk_cmt.db
+	${XRAY_MERGEDB} mask_hclk_cmt_l build/mask_hclk_cmt_l.db
+
+.PHONY: database pushdb

fuzzers/045-hclk-cmt-pips/generate.py

@@ -0,0 +1,105 @@
+#!/usr/bin/env python3
+
+from prjxray.segmaker import Segmaker
+import os
+import os.path
+
+
+def bitfilter(frame, word):
+    if frame < 26:
+        return False
+
+    return True
+
+
+def main():
+    segmk = Segmaker("design.bits")
+
+    tiledata = {}
+    pipdata = {}
+    ignpip = set()
+    tile_ports = {}
+
+    with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
+                           'hclk_cmt', 'hclk_cmt.txt')) as f:
+        for l in f:
+            tile_type, dst, src = l.strip().split('.')
+            if tile_type not in pipdata:
+                pipdata[tile_type] = []
+                tile_ports[tile_type] = set()
+
+            pipdata[tile_type].append((src, dst))
+            tile_ports[tile_type].add(src)
+            tile_ports[tile_type].add(dst)
+
+    with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
+                           'hclk_cmt', 'hclk_cmt_l.txt')) as f:
+        for l in f:
+            tile_type, dst, src = l.strip().split('.')
+            if tile_type not in pipdata:
+                pipdata[tile_type] = []
+                tile_ports[tile_type] = set()
+
+            pipdata[tile_type].append((src, dst))
+            tile_ports[tile_type].add(src)
+            tile_ports[tile_type].add(dst)
+
+    print("Loading tags from design.txt.")
+    with open("design.txt", "r") as f:
+        for line in f:
+            tile, pip, src, dst, pnum, pdir = line.split()
+
+            if not tile.startswith('HCLK_CMT'):
+                continue
+
+            pip_prefix, _ = pip.split(".")
+            tile_from_pip, tile_type = pip_prefix.split('/')
+            assert tile == tile_from_pip
+            _, src = src.split("/")
+            _, dst = dst.split("/")
+            pnum = int(pnum)
+            pdir = int(pdir)
+
+            if tile not in tiledata:
+                tiledata[tile] = {
+                    "type": tile_type,
+                    "pips": set(),
+                    "srcs": set(),
+                    "dsts": set()
+                }
+
+            tiledata[tile]["pips"].add((src, dst))
+            tiledata[tile]["srcs"].add(src)
+            tiledata[tile]["dsts"].add(dst)
+
+            if pdir == 0:
+                tiledata[tile]["srcs"].add(dst)
+                tiledata[tile]["dsts"].add(src)
+
+            if pnum == 1 or pdir == 0:
+                ignpip.add((src, dst))
+
+    for tile, pips_srcs_dsts in tiledata.items():
+        tile_type = pips_srcs_dsts["type"]
+        pips = pips_srcs_dsts["pips"]
+
+        for src, dst in pipdata[tile_type]:
+            if (src, dst) in ignpip:
+                pass
+            elif (src, dst) in pips:
+                segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
+            elif dst not in tiledata[tile]["dsts"]:
+                segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
+
+        for port in tile_ports[tile_type]:
+            if port in tiledata[tile]["dsts"] or port in tiledata[tile]["srcs"]:
+                segmk.add_tile_tag(tile, "{}_ACTIVE".format(port), 1)
+            else:
+                segmk.add_tile_tag(tile, "{}_ACTIVE".format(port), 0)
+
+    segmk.compile(bitfilter=bitfilter)
+    segmk.write()
+
+
+if __name__ == "__main__":
+    main()