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Add support for seb/seh instructions from mips32r2 (#273)
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Xeeynamo authored May 19, 2024
1 parent cdc8cdd commit 4ee07ea
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4 changes: 4 additions & 0 deletions m2c/arch_mips.py
Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,7 @@
as_intish,
as_s64,
as_sintish,
as_type,
as_u32,
as_u64,
as_uintish,
Expand Down Expand Up @@ -1662,6 +1663,9 @@ def eval_fn(s: NodeState, a: InstrArgs) -> None:
# Unaligned loads
"lwl": lambda a: handle_lwl(a),
"lwr": lambda a: handle_lwr(a),
# Sign extend
"seb": lambda a: as_type(a.reg(1), Type.s8(), silent=False),
"seh": lambda a: as_type(a.reg(1), Type.s16(), silent=False),
}

@staticmethod
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8 changes: 8 additions & 0 deletions tests/end_to_end/seb-seh/seb-mwcc-out.c
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@@ -0,0 +1,8 @@
s8 foo(s8); /* extern */

s8 test(s32 arg0) {
s32 sp10;

sp10 = arg0;
return (s8) (foo((s8) sp10) + 1);
}
19 changes: 19 additions & 0 deletions tests/end_to_end/seb-seh/seb-mwcc.s
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@@ -0,0 +1,19 @@
glabel test
addiu sp,sp,-0x20
sw ra,0xc(sp)
sw s0,8(sp)
sw a0,0x10(sp)
lw v0,0x10(sp)
seb a0,v0
jal foo
nop
seb v0,v0
addiu v0,v0,1
seb v0,v0
seb s0,v0
move v0,s0
lw ra,0xc(sp)
lw s0,8(sp)
addiu sp,sp,0x20
jr ra
nop
8 changes: 8 additions & 0 deletions tests/end_to_end/seb-seh/seh-mwcc-out.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
s16 foo(s16); /* extern */

s16 test(s32 arg0) {
s32 sp10;

sp10 = arg0;
return (s16) (foo((s16) sp10) + 1);
}
19 changes: 19 additions & 0 deletions tests/end_to_end/seb-seh/seh-mwcc.s
Original file line number Diff line number Diff line change
@@ -0,0 +1,19 @@
glabel test
addiu sp,sp,-0x20
sw ra,0xc(sp)
sw s0,8(sp)
sw a0,0x10(sp)
lw v0,0x10(sp)
seh a0,v0
jal foo
nop
seh v0,v0
addiu v0,v0,1
seh v0,v0
seh s0,v0
move v0,s0
lw ra,0xc(sp)
lw s0,8(sp)
addiu sp,sp,0x20
jr ra
nop

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