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[dv,top_earlgrey] Fix pwrmgr_rstmgr_sva_if bind for top
The assertions pwrmgr_rstmgr_sva_if need to be disabled when either aon or main_pok are inactive. It is more reliable to bind them to rstmgr for top-level simulations. This PR does that and connects rst_slow_ni to &rst_por_aon_n, since rst_por_aon_n is 2-bit wide (one per domain), and captures the rstmgr behavior more accurately. This also removes the rstmgr_unit_only* files for simplicity. Fixes lowRISC#23961 Signed-off-by: Guillermo Maturana <[email protected]>
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Original file line number | Diff line number | Diff line change |
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// Copyright lowRISC contributors (OpenTitan project). | ||
// Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
// SPDX-License-Identifier: Apache-2.0 | ||
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// This binds assertions that should not be bound at chip level. | ||
module pwrmgr_unit_only_bind; | ||
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bind pwrmgr pwrmgr_rstmgr_sva_if pwrmgr_rstmgr_sva_if ( | ||
.clk_i, | ||
.rst_ni, | ||
.clk_slow_i, | ||
.rst_slow_ni, | ||
// The outputs from pwrmgr. | ||
.rst_lc_req(pwr_rst_o.rst_lc_req), | ||
.rst_sys_req(pwr_rst_o.rst_sys_req), | ||
// The inputs from rstmgr. | ||
.rst_lc_src_n(pwr_rst_i.rst_lc_src_n), | ||
.rst_sys_src_n(pwr_rst_i.rst_sys_src_n) | ||
); | ||
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endmodule : pwrmgr_unit_only_bind |
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21 changes: 21 additions & 0 deletions
21
hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_bind.sv
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Original file line number | Diff line number | Diff line change |
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// Copyright lowRISC contributors (OpenTitan project). | ||
// Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
// SPDX-License-Identifier: Apache-2.0 | ||
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// This binds assertions that should not be bound at chip level. | ||
module pwrmgr_unit_only_bind; | ||
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bind pwrmgr pwrmgr_rstmgr_sva_if pwrmgr_rstmgr_sva_if ( | ||
.clk_i, | ||
.rst_ni, | ||
.clk_slow_i, | ||
.rst_slow_ni, | ||
// The outputs from pwrmgr. | ||
.rst_lc_req(pwr_rst_o.rst_lc_req), | ||
.rst_sys_req(pwr_rst_o.rst_sys_req), | ||
// The inputs from rstmgr. | ||
.rst_lc_src_n(pwr_rst_i.rst_lc_src_n), | ||
.rst_sys_src_n(pwr_rst_i.rst_sys_src_n) | ||
); | ||
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endmodule : pwrmgr_unit_only_bind |
39 changes: 39 additions & 0 deletions
39
hw/top_earlgrey/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_sva.core
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CAPI=2: | ||
# Copyright lowRISC contributors (OpenTitan project). | ||
# Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
# SPDX-License-Identifier: Apache-2.0 | ||
name: "lowrisc:dv:pwrmgr_unit_only_sva:0.1" | ||
gdescription: "PWRMGR assertion interfaces not suitable for chip level bind file." | ||
filesets: | ||
files_dv: | ||
depend: | ||
- lowrisc:tlul:headers | ||
- lowrisc:fpv:csr_assert_gen | ||
- lowrisc:dv:pwrmgr_rstmgr_sva_if | ||
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files: | ||
- pwrmgr_unit_only_bind.sv | ||
file_type: systemVerilogSource | ||
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files_formal: | ||
depend: | ||
- lowrisc:ip_interfaces:pwrmgr | ||
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generate: | ||
csr_assert_gen: | ||
generator: csr_assert_gen | ||
parameters: | ||
spec: ../../data/pwrmgr.hjson | ||
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targets: | ||
default: &default_target | ||
filesets: | ||
- files_dv | ||
generate: | ||
- csr_assert_gen | ||
formal: | ||
<<: *default_target | ||
filesets: | ||
- files_formal | ||
- files_dv | ||
toplevel: pwrmgr |
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