WIP to enable stm32u0

repo.lb

@@ -87,7 +87,7 @@ class DevicesCache(dict):
                      "stm32g0", "stm32g4",
                      "stm32h7",
                      "stm32l0", "stm32l1", "stm32l4", "stm32l5",
-                     "stm32u5",
+                     "stm32u0", "stm32u5",
                      "at90", "attiny", "atmega",
                      "samd21", "samg55",
                      "same70", "sams70", "samv70", "samv71",

src/modm/board/disco_u083c/board.xml

@@ -6,7 +6,7 @@
   </repositories>
 
   <options>
-    <option name="modm:target">stm32u83mct6</option>
+    <option name="modm:target">stm32u083mct6</option>
   </options>
   <modules>
     <module>modm:board:disco-u083c</module>

src/modm/platform/adc/stm32/module.lb

@@ -79,7 +79,7 @@ def prepare(module, options):
     if target["family"] in ["f2", "f4", "f7"]:
         props["shared_irqs"] = {"ADC": listify([int(i) for i in device.get_driver("adc")["instance"]])}
         props["shared_irq_ids"] = props["shared_irqs"]["ADC"]
-    elif target["family"] in ["u5"]:
+    elif target["family"] in ["u5", "u0"]:
         # STM32U5 is not yet supported with any ADC implementation im modm
         return False
     else:

src/modm/platform/clock/stm32/rcc.hpp.in

@@ -86,7 +86,7 @@ public:
 		InternalClock = Hsi16,
 		/// High speed external clock
 		Hse = RCC_CFGR_PLLSRC,
-%% elif target.family == "l5"
+%% elif target.family in ["l5", "u0"]
 		/// High speed internal clock (16 MHz)
 		Hsi = RCC_PLLCFGR_PLLSRC_1,
 		Hsi16 = Hsi,
@@ -134,7 +134,7 @@ public:
 	enum class
 	SystemClockSource : uint32_t
 	{
-%% if target.family == "l5"
+%% if target.family in ["l5", "u0"]
 		Msi = 0,
 		Hsi = RCC_CFGR_SW_0,
 		Hsi16 = Hsi,
@@ -194,7 +194,7 @@ public:
 	enum class
 	AhbPrescaler : uint32_t
 	{
-%% if target.family in ["l5", "u5"]
+%% if target.family in ["l5", "u0", "u5"]
 		Div1   = 0b0000 << RCC_{{cfgr_prescaler}}_HPRE_Pos,
 		Div2   = 0b1000 << RCC_{{cfgr_prescaler}}_HPRE_Pos,
 		Div4   = 0b1001 << RCC_{{cfgr_prescaler}}_HPRE_Pos,
@@ -237,6 +237,12 @@ public:
 		Div4   = 0b101 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE1_Pos,
 		Div8   = 0b110 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE1_Pos,
 		Div16  = 0b111 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE1_Pos
+%% elif target.family == "u0"
+		Div1   = 0b000 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE_Pos,
+		Div2   = 0b100 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE_Pos,
+		Div4   = 0b101 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE_Pos,
+		Div8   = 0b110 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE_Pos,
+		Div16  = 0b111 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE_Pos
 %% else
 		Div1   = RCC_{{cfgr2}}_{{d2}}PPRE1_DIV1,
 		Div2   = RCC_{{cfgr2}}_{{d2}}PPRE1_DIV2,
@@ -255,6 +261,7 @@ public:
 		Div4   = 0b101 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE2_Pos,
 		Div8   = 0b110 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE2_Pos,
 		Div16  = 0b111 << RCC_{{cfgr_prescaler}}_{{d2}}PPRE2_Pos
+%% elif target.family == "u0"
 %% else
 		Div1   = RCC_{{cfgr2}}_{{d2}}PPRE2_DIV1,
 		Div2   = RCC_{{cfgr2}}_{{d2}}PPRE2_DIV2,
@@ -355,6 +362,7 @@ public:
 	};
 %% endif
 
+%% set cfgr_mco="CFGR1" if target.family in ["u5"] else "CFGR"
 %% if target.family in ["f2", "f4", "f7"]
 	enum class
 	ClockOutput1Source : uint32_t
@@ -397,7 +405,6 @@ public:
 		Lsi = RCC_CFGR_MCO2_2 | RCC_CFGR_MCO2_0
 	};
 %% elif target.family in ["l0", "l1", "l4", "l5", "g0", "g4", "u5"]
-%% set cfgr_mco="CFGR1" if target.family in ["u5"] else "CFGR"
 	enum class
 	ClockOutputSource : uint32_t
 	{
@@ -426,6 +433,15 @@ public:
 		MultiSpeedInternalClockK = (0b1001 << RCC_{{cfgr_mco}}_MCOSEL_Pos), // MSIK
 	%% endif
 	};
+%% elif target.family == "u0"
+	enum class
+		ClockOutputSource : uint32_t
+		{
+		Disable = 0b0000,
+		SystemClock = (0b0001 << RCC_CFGR_MCO1SEL_Pos), // SYSCLK
+		LowSpeedInternalClock = (0b0110 << RCC_CFGR_MCO1SEL_Pos), // LSI
+		LowSpeedExternalClock = (0b0111 << RCC_CFGR_MCO1SEL_Pos), // LSE
+	};
 %% else
 	enum class
 	ClockOutputSource : uint32_t
@@ -835,7 +851,7 @@ public:
 		RCC->CFGR = tmp | uint32_t(src);
 		return true;
 	}
-%% elif target.family in ["l0", "l1", "l4", "l5", "g0", "g4", "u5"]
+%% elif target.family in ["l0", "l1", "l4", "l5", "g0", "g4", "u0", "u5"]
 	enum class
 	ClockOutputPrescaler : uint32_t
 	{

src/modm/platform/core/stm32/module.lb

@@ -59,6 +59,7 @@ def build(env):
         "g4": (3,  4), # CM4  tested on G476 in RAM
         "l0": (3,  4), # CM0+ tested on L031 in RAM
         "g0": (3,  4), # CM0+ tested on G072 in RAM
+        "u0": (3,  4), # CM0+ untested
         "f7": (4,  4), # CM7  tested on F767 in ITCM
         "h7": (4,  4), # CM7  tested on H743 in ITCM
         "l4": (3,  4), # CM4  tested on L476 in SRAM2

src/modm/platform/core/stm32/startup_platform.c.in

@@ -35,6 +35,8 @@ __modm_initialize_platform(void)
 	RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
 %% elif target.family == "h7"
 	RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;
+%% elif target.family == "u0"
+	RCC->AHBENR |= RCC_APBENR2_SYSCFGEN;
 %% elif target.family == "u5"
 	RCC->APB3ENR |= RCC_APB3ENR_SYSCFGEN;
 %% else

src/modm/platform/gpio/stm32/enable.cpp.in

@@ -28,7 +28,7 @@ modm_gpio_enable(void)
 %%	set prefix = "IOP"
 %% elif target.family in ["l4", "l5", "g4", "u5"]
 %%  set clock_tree = 'AHB2'
-%% elif target.family in ["g0", "l0"]
+%% elif target.family in ["g0", "l0", "u0"]
 %%  set clock_tree = 'IOP'
 %% endif