Fixed branching bugs

resources/core-instructions.csv

@@ -1,62 +1,62 @@
 name,mnemonic,format,opCode,argsFormat,args,argTypes
+ADD,ADD,R,458,"_, _, _",013,rrr
+ADD Immediate,ADDI,I,488-489,"_, _, _",012,rri
+ADD Immediate & Set flags,ADDIS,I,588-589,"_, _, _",012,rri
+ADD & Set flags,ADDS,R,558,"_, _, _",013,rrr
+AND,AND,R,450,"_, _, _",013,rrr
+AND Immediate,ANDI,I,490-491,"_, _, _",012,rri
+AND Immediate & Set flags,ANDIS,I,790-791,"_, _, _",012,rri
+AND & Set flags,ANDS,R,750,"_, _, _",013,rrr
 Branch unconditionally,B,B,0A0-0BF,_,0,l
-Branch with Link,BL,B,4A0-4BF,_,1,l
 Branch conditionally (equal),B.EQ,CB,2A0,_,1,l
-Branch conditionally (not equal),B.NE,CB,2A1,_,1,l
-Branch conditionally (less than),B.LT,CB,2AB,_,1,l
-Branch conditionally (less than or equal),B.LE,CB,2AD,_,1,l
-Branch conditionally (greater than),B.GT,CB,2AC,_,1,l
 Branch conditionally (greater than or equal),B.GE,CB,2AA,_,1,l
+Branch conditionally (greater than),B.GT,CB,2AC,_,1,l
 Branch conditionally (higher),B.HI,CB,2A8,_,1,l
 Branch conditionally (higher or same),B.HS,CB,2A2,_,1,l
+Branch conditionally (less than or equal),B.LE,CB,2AD,_,1,l
 Branch conditionally (lower),B.LO,CB,2A3,_,1,l
 Branch conditionally (lower or same),B.LS,CB,2A9,_,1,l
+Branch conditionally (less than),B.LT,CB,2AB,_,1,l
 Branch conditionally (on minus),B.MI,CB,2A4,_,1,l
+Branch conditionally (not equal),B.NE,CB,2A1,_,1,l
 Branch conditionally (on plus),B.PL,CB,2A5,_,1,l
-Branch conditionally (on overflow set),B.VS,CB,2A7,_,1,l
 Branch conditionally (on overflow clear),B.VC,CB,2A8,_,1,l
+Branch conditionally (on overflow set),B.VS,CB,2A7,_,1,l
+Branch with Link,BL,B,4A0-4BF,_,0,l
+Branch to Register,BR,R,6B0,_,0,r
 Compare & Branch if Not Zero,CBNZ,CB,5A8-5AF,"_, _",01,rl
 Compare & Branch if Zero,CBZ,CB,5A0-5A7,"_, _",01,rl
+CoMPare,CMP,R,0,"_, _",01,rr
+CoMPare Immediate,CMPI,I,0,"_, _",01,ri
+Dump,DUMP,Z,0,,,
+Exclusive OR,EOR,R,650,"_, _, _",013,rrr
+Exclusive OR Immediate,EORI,I,690-691,"_, _, _",012,rri
+LoaD Address,LDA,D,0,"_, _",01,ri
 LoaD Register Unscaled offset,LDUR,D,7C2,"_, [_, _]",012,rri
 LoaD Byte Unscaled offset,LDURB,D,1C2,"_, [_, _]",012,rri
 LoaD Half Unscaled offset,LDURH,D,3C2,"_, [_, _]",012,rri
 LoaD Signed Word Unscaled offset,LDURSW,D,5C4,"_, [_, _]",012,rri
 LoaD eXclusive Register,LDXR,D,642,"_, [_, _]",012,rri
+Logical Shift Left,LSL,R,69B,"_, _, _",012,rri
+Logical Shift Right,LSR,R,69A,"_, _, _",012,rri
+MOVe,MOV,R,0,"_, _",01,rr
+MOVe wide with Keep,MOVK,IM,794-797,"_, _",01,ri
+MOVe wide with Zero,MOVZ,IM,694-697,"_, _",01,ri
+MULtiply,MUL,R,4D8,"_, _, _",013,rrr
+Inclusive OR,ORR,R,550,"_, _, _",013,rrr
+Inclusive OR Immediate,ORRI,I,590-591,"_, _, _",012,rri
+PRiNt Line,PRNL,Z,0,,,
+PRiNT register,PRNT,Z,0,_,0,r
+Signed DIVide,SDIV,R,4D6,"_, _, _",013,rrr
+Signed MULtiply High,SMULH,R,4DA,"_, _, _",013,rrr
 STore Register Unscaled offset,STUR,D,7C0,"_, [_, _]",012,rri
 STore Byte Unscaled offset,STURB,D,1C0,"_, [_, _]",012,rri
 STore Half Unscaled offset,STURH,D,3C0,"_, [_, _]",012,rri
 STore Word Unscaled offset,STURW,D,5C0,"_, [_, _]",012,rri
 STore eXclusive Register,STXR,D,640,"_, [_, _]",012,rri
-LoaD Address,LDA,D,0,"_, _",01,ri
-ADD Immediate,ADDI,I,488-489,"_, _, _",012,rri
-ADD Immediate & Set flags,ADDIS,I,588-589,"_, _, _",012,rri
-AND Immediate,ANDI,I,490-491,"_, _, _",012,rri
-AND Immediate & Set flags,ANDIS,I,790-791,"_, _, _",012,rri
-Exclusive OR Immediate,EORI,I,690-691,"_, _, _",012,rri
-Inclusive OR Immediate,ORRI,I,590-591,"_, _, _",012,rri
+SUBtract,SUB,R,658,"_, _, _",013,rrr
 SUBtract Immediate,SUBI,I,688-689,"_, _, _",012,rri
 SUBtract Immediate & Set flags,SUBIS,I,788-789,"_, _, _",012,rri
-CoMPare Immediate,CMPI,I,0,"_, _",01,ri
-MOVe wide with Keep,MOVK,IM,794-797,"_, _",01,ri
-MOVe wide with Zero,MOVZ,IM,694-697,"_, _",01,ri
-ADD,ADD,R,458,"_, _, _",013,rrr
-ADD & Set flags,ADDS,R,558,"_, _, _",013,rrr
-AND,AND,R,450,"_, _, _",013,rrr
-AND & Set flags,ANDS,R,750,"_, _, _",013,rrr
-Branch to Register,BR,R,6B0,_,0,r
-Exclusive OR,EOR,R,650,"_, _, _",013,rrr
-Logical Shift Left,LSL,R,69B,"_, _, _",012,rri
-Logical Shift Right,LSR,R,69A,"_, _, _",012,rri
-Inclusive OR,ORR,R,550,"_, _, _",013,rrr
-SUBtract,SUB,R,658,"_, _, _",013,rrr
 SUBtract & Set flags,SUBS,R,758,"_, _, _",013,rrr
-MULtiply,MUL,R,4D8,"_, _, _",013,rrr
-Signed DIVide,SDIV,R,4D6,"_, _, _",013,rrr
-Signed MULtiply High,SMULH,R,4DA,"_, _, _",013,rrr
 Unsigned DIVide,UDIV,R,4D6,"_, _, _",013,rrr
-Unsigned MULtiply High,UMULH,R,4DE,"_, _, _",013,rrr
-CoMPare,CMP,R,0,"_, _",01,rr
-MOVe,MOV,R,0,"_, _",01,rr
-Dump,DUMP,Z,0,,,
-PRiNT register,PRNT,Z,0,_,0,r
-PRiNt Line,PRNL,Z,0,,,
+Unsigned MULtiply High,UMULH,R,4DE,"_, _, _",013,rrr

src/BInstruction.ts

@@ -16,7 +16,7 @@ export class BInstruction extends Instruction {
                 sim.branch(this.getBrAddress());
                 break;
             case InstructionMnemonic.BL:
-                sim.setReg(Simulation.lrRegister, sim.index() + 1);
+                sim.setReg(Simulation.lrRegister, sim.index());
                 sim.branch(this.getBrAddress());
                 break;
             default:

src/CoreInstruction.ts

@@ -160,7 +160,7 @@ export class CoreInstruction {
 
                     // if undefined, the argument is invalid
                     if (arg === undefined) {
-                        Output.error(`Invalid argument "${argStr}" from ${i} to ${i + lineIndex} on line: ${line.toString()}`);
+                        Output.error(`Invalid argument "${argStr}" on line: ${line.toString()}`);
                         return undefined;
                     }
 

src/Instruction.ts

@@ -16,13 +16,16 @@ export class Instruction {
         this._mnemonic = line.getLabel().toUpperCase() as InstructionMnemonic;
 
         // get the argument values
-        let values = core.extractArgValuesFromLine(line);
-
         // pack into data
         this._code = new PackedNumber(0);
 
-        if (values !== undefined) {
-            this.setCodes(core, values);
+        // get the argument values
+        if (line.getArgs().length !== 0) {
+            let values = core.extractArgValuesFromLine(line);
+
+            if (values !== undefined) {
+                this.setCodes(core, values);
+            }
         }
     }
 

src/Output.ts

@@ -17,7 +17,9 @@ export class Output {
     }
 
     public static error(text: string): void {
-        this.writeLine("ERROR: " + text);
+        const t = "ERROR: " + text;
+        this.writeLine(t);
+        console.log(t);
     }
 
     public static write(text: string): void {

src/ZInstruction.ts

@@ -8,7 +8,8 @@ export class ZInstruction extends Instruction {
     private extra: string;
 
     public constructor(core: CoreInstruction, line: Line) {
-        super(core, line);
+        // ignore args so super class does not parse it
+        super(core, new Line(line.getLabel(), line.getLineNumber()));
 
         this.extra = line.getArgs();
     }

src/extension.ts

@@ -27,8 +27,7 @@ export function activate(context: vscode.ExtensionContext) {
 
 		if (editor) {
 			Output.show();
-
-			Output.write("Test");
+			Output.clear();
 
 			const document = editor.document;
 			const start = editor.selection.start;
@@ -44,8 +43,9 @@ export function activate(context: vscode.ExtensionContext) {
 				sim = Parser.parseSimulation(document.getText(new vscode.Range(start, end)));
 			}
 
+			console.log("Program start.");
 			sim.run();
-			console.log(`Program executed in ${sim.executionTime()}ms.`);
+			console.log(`Program stop. Executed in ${sim.executionTime()}ms.`);
 		}
 
 		//vscode.window.showInformationMessage('Hello World from LEGv8 Assembly!');
@@ -125,6 +125,7 @@ export function activate(context: vscode.ExtensionContext) {
 
 				const c = new vscode.CompletionItem(preview);
 				c.insertText = new vscode.SnippetString(sb);
+				c.commitCharacters = ['\t', '\r', '\n', '\r\n'];
 
 				completionItems.push(c);
 			}

syntaxes/LEGv8.tmLanguage.json

@@ -60,7 +60,7 @@
         },
         "label": {
             "name": "entity.name.tag",
-            "match": "\\b^([a-z]|[A-Z]|_)+:",
+            "match": "\\b^([a-z]|[A-Z]|_|[0-9])+:",
             "patterns": [
                 {
                     "include": "#comment"
@@ -107,7 +107,7 @@
         },
         "branchLabel": {
             "name": "entity.name.tag",
-            "match": "\\b([a-z]|[A-Z]|_)+\\b"
+            "match": "\\b([a-z]|[A-Z]|_|[0-9])+\\b"
         },
         "comment": {
             "name": "comment.LEGv8",