Skip to content

Commit

Permalink
update
Browse files Browse the repository at this point in the history
  • Loading branch information
@mthudaaa
mthudaaa committed Oct 31, 2024
1 parent 6e73138 commit 005fa2a
Show file tree
Hide file tree
Showing 5 changed files with 85 additions and 72 deletions.
18 changes: 10 additions & 8 deletions xschem/10b_adc.sch
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,13 @@ C {devices/lab_wire.sym} 720 -380 0 0 {name=p4 sig_type=std_logic lab=VSSA}
C {devices/lab_wire.sym} 280 -180 0 0 {name=p5 sig_type=std_logic lab=VSSR}
C {devices/lab_wire.sym} 280 -360 0 0 {name=p6 sig_type=std_logic lab=VSSA}
C {devices/lab_wire.sym} 720 -280 0 0 {name=p7 sig_type=std_logic lab=VDDD}
C {devices/lab_wire.sym} 720 -200 0 0 {name=p8 sig_type=std_logic lab=VSSD}
C {devices/lab_wire.sym} 720 -180 0 0 {name=p8 sig_type=std_logic lab=VSSD}
C {devices/lab_wire.sym} 280 -420 0 0 {name=p9 sig_type=std_logic lab=CLKS}
C {devices/lab_wire.sym} 280 -440 0 0 {name=p10 sig_type=std_logic lab=CLKSB}
C {devices/lab_wire.sym} 1020 -280 0 1 {name=p11 sig_type=std_logic lab=CLKS}
C {devices/lab_wire.sym} 1020 -260 0 1 {name=p12 sig_type=std_logic lab=CLKSB}
C {devices/lab_wire.sym} 720 -220 0 0 {name=p15 sig_type=std_logic lab=COMP_N}
C {devices/lab_wire.sym} 720 -260 0 0 {name=p17 sig_type=std_logic lab=CLK}
C {devices/lab_wire.sym} 720 -200 0 0 {name=p15 sig_type=std_logic lab=COMP_N}
C {devices/lab_wire.sym} 720 -240 0 0 {name=p17 sig_type=std_logic lab=CLK}
C {devices/lab_wire.sym} 580 -460 0 1 {name=p18 sig_type=std_logic lab=VCP}
C {devices/lab_wire.sym} 580 -440 0 1 {name=p19 sig_type=std_logic lab=VCN}
C {devices/lab_wire.sym} 580 -280 0 1 {name=p20 sig_type=std_logic lab=VCP}
Expand All @@ -39,9 +39,9 @@ C {devices/lab_wire.sym} 1020 -220 0 1 {name=p33 sig_type=std_logic lab=SWP[0:9]
C {devices/lab_wire.sym} 1020 -200 0 1 {name=p34 sig_type=std_logic lab=SWN[0:9]}
C {devices/lab_wire.sym} 1020 -160 0 1 {name=p35 sig_type=std_logic lab=CKO}
C {devices/lab_wire.sym} 1020 -180 0 1 {name=p36 sig_type=std_logic lab=DOUT[0:9]}
C {devices/ipin.sym} 80 -480 0 0 {name=p37 sig_type=std_logic lab=VDDA}
C {devices/ipin.sym} 80 -460 0 0 {name=p38 sig_type=std_logic lab=VDDD}
C {devices/ipin.sym} 80 -440 0 0 {name=p39 sig_type=std_logic lab=VCM}
C {devices/ipin.sym} 80 -500 0 0 {name=p37 sig_type=std_logic lab=VDDA}
C {devices/ipin.sym} 80 -480 0 0 {name=p38 sig_type=std_logic lab=VDDD}
C {devices/ipin.sym} 80 -460 0 0 {name=p39 sig_type=std_logic lab=VCM}
C {devices/ipin.sym} 80 -420 0 0 {name=p40 sig_type=std_logic lab=CLK}
C {devices/ipin.sym} 80 -400 0 0 {name=p41 sig_type=std_logic lab=VIP}
C {devices/ipin.sym} 80 -380 0 0 {name=p42 sig_type=std_logic lab=VIN}
Expand All @@ -52,7 +52,9 @@ C {devices/opin.sym} 60 -220 0 0 {name=p46 sig_type=std_logic lab=CKO}
C {cdac_10b.sym} 430 -230 0 0 {name=x1}
C {tdc.sym} 870 -420 0 0 {name=x3}
C {devices/ipin.sym} 80 -360 0 0 {name=p14 sig_type=std_logic lab=VSSR}
C {devices/ipin.sym} 80 -500 0 0 {name=p16 sig_type=std_logic lab=VDDR}
C {devices/lab_wire.sym} 720 -240 0 0 {name=p24 sig_type=std_logic lab=COMP_P}
C {devices/ipin.sym} 80 -520 0 0 {name=p16 sig_type=std_logic lab=VDDR}
C {devices/lab_wire.sym} 720 -220 0 0 {name=p24 sig_type=std_logic lab=COMP_P}
C {devices/lab_wire.sym} 1020 -460 0 1 {name=p13 sig_type=std_logic lab=COMP_P}
C {devices/lab_wire.sym} 1020 -440 0 1 {name=p48 sig_type=std_logic lab=COMP_N}
C {devices/lab_wire.sym} 720 -260 0 0 {name=p47 sig_type=std_logic lab=EN}
C {devices/ipin.sym} 80 -440 0 0 {name=p49 sig_type=std_logic lab=EN}
85 changes: 44 additions & 41 deletions xschem/10b_adc.sym
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,44 +4,47 @@ format="@name @pinlist @symname"
template="name=x1"
}
T {@symname} -49.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -112 0 0 0.2 0.2 {}
L 4 -130 -100 130 -100 {}
L 4 -130 100 130 100 {}
L 4 -130 -100 -130 100 {}
L 4 130 -100 130 100 {}
B 5 -152.5 -92.5 -147.5 -87.5 {name=VDDR sig_type=std_logic dir=in}
L 4 -150 -90 -130 -90 {}
T {VDDR} -125 -94 0 0 0.2 0.2 {}
B 5 -152.5 -72.5 -147.5 -67.5 {name=VDDA sig_type=std_logic dir=in}
L 4 -150 -70 -130 -70 {}
T {VDDA} -125 -74 0 0 0.2 0.2 {}
B 5 -152.5 -52.5 -147.5 -47.5 {name=VDDD sig_type=std_logic dir=in}
L 4 -150 -50 -130 -50 {}
T {VDDD} -125 -54 0 0 0.2 0.2 {}
B 5 -152.5 -32.5 -147.5 -27.5 {name=VCM sig_type=std_logic dir=in}
L 4 -150 -30 -130 -30 {}
T {VCM} -125 -34 0 0 0.2 0.2 {}
B 5 -152.5 -12.5 -147.5 -7.5 {name=CLK sig_type=std_logic dir=in}
L 4 -150 -10 -130 -10 {}
T {CLK} -125 -14 0 0 0.2 0.2 {}
B 5 -152.5 7.5 -147.5 12.5 {name=VIP sig_type=std_logic dir=in}
L 4 -150 10 -130 10 {}
T {VIP} -125 6 0 0 0.2 0.2 {}
B 5 -152.5 27.5 -147.5 32.5 {name=VIN sig_type=std_logic dir=in}
L 4 -150 30 -130 30 {}
T {VIN} -125 26 0 0 0.2 0.2 {}
B 5 -152.5 47.5 -147.5 52.5 {name=VSSR sig_type=std_logic dir=in}
L 4 -150 50 -130 50 {}
T {VSSR} -125 46 0 0 0.2 0.2 {}
B 5 -152.5 67.5 -147.5 72.5 {name=VSSA sig_type=std_logic dir=in}
L 4 -150 70 -130 70 {}
T {VSSA} -125 66 0 0 0.2 0.2 {}
B 5 -152.5 87.5 -147.5 92.5 {name=VSSD sig_type=std_logic dir=in}
L 4 -150 90 -130 90 {}
T {VSSD} -125 86 0 0 0.2 0.2 {}
B 5 147.5 -92.5 152.5 -87.5 {name=DOUT[0:9] sig_type=std_logic dir=out}
L 4 130 -90 150 -90 {}
T {DOUT[0:9]} 125 -94 0 1 0.2 0.2 {}
B 5 147.5 -72.5 152.5 -67.5 {name=CKO sig_type=std_logic dir=out}
L 4 130 -70 150 -70 {}
T {CKO} 125 -74 0 1 0.2 0.2 {}
T {@name} 135 -122 0 0 0.2 0.2 {}
L 4 -130 -110 130 -110 {}
L 4 -130 110 130 110 {}
L 4 -130 -110 -130 110 {}
L 4 130 -110 130 110 {}
B 5 -152.5 -102.5 -147.5 -97.5 {name=VDDR sig_type=std_logic dir=in}
L 4 -150 -100 -130 -100 {}
T {VDDR} -125 -104 0 0 0.2 0.2 {}
B 5 -152.5 -82.5 -147.5 -77.5 {name=VDDA sig_type=std_logic dir=in}
L 4 -150 -80 -130 -80 {}
T {VDDA} -125 -84 0 0 0.2 0.2 {}
B 5 -152.5 -62.5 -147.5 -57.5 {name=VDDD sig_type=std_logic dir=in}
L 4 -150 -60 -130 -60 {}
T {VDDD} -125 -64 0 0 0.2 0.2 {}
B 5 -152.5 -42.5 -147.5 -37.5 {name=VCM sig_type=std_logic dir=in}
L 4 -150 -40 -130 -40 {}
T {VCM} -125 -44 0 0 0.2 0.2 {}
B 5 -152.5 -22.5 -147.5 -17.5 {name=EN sig_type=std_logic dir=in}
L 4 -150 -20 -130 -20 {}
T {EN} -125 -24 0 0 0.2 0.2 {}
B 5 -152.5 -2.5 -147.5 2.5 {name=CLK sig_type=std_logic dir=in}
L 4 -150 0 -130 0 {}
T {CLK} -125 -4 0 0 0.2 0.2 {}
B 5 -152.5 17.5 -147.5 22.5 {name=VIP sig_type=std_logic dir=in}
L 4 -150 20 -130 20 {}
T {VIP} -125 16 0 0 0.2 0.2 {}
B 5 -152.5 37.5 -147.5 42.5 {name=VIN sig_type=std_logic dir=in}
L 4 -150 40 -130 40 {}
T {VIN} -125 36 0 0 0.2 0.2 {}
B 5 -152.5 57.5 -147.5 62.5 {name=VSSR sig_type=std_logic dir=in}
L 4 -150 60 -130 60 {}
T {VSSR} -125 56 0 0 0.2 0.2 {}
B 5 -152.5 77.5 -147.5 82.5 {name=VSSA sig_type=std_logic dir=in}
L 4 -150 80 -130 80 {}
T {VSSA} -125 76 0 0 0.2 0.2 {}
B 5 -152.5 97.5 -147.5 102.5 {name=VSSD sig_type=std_logic dir=in}
L 4 -150 100 -130 100 {}
T {VSSD} -125 96 0 0 0.2 0.2 {}
B 5 147.5 -102.5 152.5 -97.5 {name=DOUT[0:9] sig_type=std_logic dir=out}
L 4 130 -100 150 -100 {}
T {DOUT[0:9]} 125 -104 0 1 0.2 0.2 {}
B 5 147.5 -82.5 152.5 -77.5 {name=CKO sig_type=std_logic dir=out}
L 4 130 -80 150 -80 {}
T {CKO} 125 -84 0 1 0.2 0.2 {}
30 changes: 17 additions & 13 deletions xschem/adc_tb.sch
View file
Original file line number Diff line number Diff line change
Expand Up @@ -78,12 +78,12 @@ C {devices/gnd.sym} 590 -80 0 0 {name=l1 lab=GND}
C {devices/lab_wire.sym} 590 -140 0 0 {name=p1 sig_type=std_logic lab=VSSA}
C {devices/lab_wire.sym} 700 -230 2 1 {name=p2 sig_type=std_logic lab=VSSA}
C {devices/lab_wire.sym} 780 -230 2 1 {name=p3 sig_type=std_logic lab=VSSD}
C {devices/lab_wire.sym} 540 -430 0 0 {name=p6 sig_type=std_logic lab=VSSA}
C {devices/lab_wire.sym} 540 -420 0 0 {name=p6 sig_type=std_logic lab=VSSA}
C {devices/lab_wire.sym} 700 -290 0 0 {name=p7 sig_type=std_logic lab=VDDA}
C {devices/lab_wire.sym} 540 -570 0 0 {name=p8 sig_type=std_logic lab=VDDA}
C {devices/lab_wire.sym} 540 -550 0 0 {name=p9 sig_type=std_logic lab=VDDD}
C {devices/lab_wire.sym} 540 -580 0 0 {name=p8 sig_type=std_logic lab=VDDA}
C {devices/lab_wire.sym} 540 -560 0 0 {name=p9 sig_type=std_logic lab=VDDD}
C {devices/lab_wire.sym} 780 -290 0 0 {name=p10 sig_type=std_logic lab=VDDD}
C {devices/lab_wire.sym} 540 -510 0 0 {name=p12 sig_type=std_logic lab=CLK}
C {devices/lab_wire.sym} 540 -500 0 0 {name=p12 sig_type=std_logic lab=CLK}
C {devices/vsource.sym} 540 -260 0 0 {name=VC value=0.9 savecurrent=false}
C {devices/lab_wire.sym} 540 -230 2 1 {name=p13 sig_type=std_logic lab=VSSR}
C {devices/lab_wire.sym} 540 -290 0 0 {name=p14 sig_type=std_logic lab=VCM}
Expand All @@ -93,19 +93,19 @@ C {devices/vsource.sym} 260 -180 0 0 {name=VSS3 value=0.9 savecurrent=false}
C {devices/lab_wire.sym} 200 -350 0 0 {name=p15 sig_type=std_logic lab=VIP}
C {devices/lab_wire.sym} 320 -350 0 0 {name=p16 sig_type=std_logic lab=VIN}
C {devices/lab_wire.sym} 260 -150 2 0 {name=p17 sig_type=std_logic lab=VSSR}
C {devices/lab_wire.sym} 540 -490 0 0 {name=p18 sig_type=std_logic lab=VIP}
C {devices/lab_wire.sym} 540 -470 0 0 {name=p19 sig_type=std_logic lab=VIN}
C {devices/lab_wire.sym} 540 -450 0 0 {name=p5 sig_type=std_logic lab=VSSR}
C {devices/lab_wire.sym} 540 -530 0 0 {name=p20 sig_type=std_logic lab=VCM}
C {devices/lab_wire.sym} 840 -590 0 1 {name=p21 sig_type=std_logic lab=DOUT[0:9]}
C {devices/lab_wire.sym} 840 -570 0 1 {name=p22 sig_type=std_logic lab=CKO}
C {devices/lab_wire.sym} 540 -480 0 0 {name=p18 sig_type=std_logic lab=VIP}
C {devices/lab_wire.sym} 540 -460 0 0 {name=p19 sig_type=std_logic lab=VIN}
C {devices/lab_wire.sym} 540 -440 0 0 {name=p5 sig_type=std_logic lab=VSSR}
C {devices/lab_wire.sym} 540 -540 0 0 {name=p20 sig_type=std_logic lab=VCM}
C {devices/lab_wire.sym} 840 -600 0 1 {name=p21 sig_type=std_logic lab=DOUT[0:9]}
C {devices/lab_wire.sym} 840 -580 0 1 {name=p22 sig_type=std_logic lab=CKO}
C {devices/code.sym} 185 -565 0 0 {name=TT_MODELS
only_toplevel=true
format="tcleval( @value )"
value="
** opencircuitdesign pdks install
* .lib $::SKYWATER_MODELS/sky130.lib.spice tt
.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hdll/spice/sky130_fd_sc_hdll.spice
.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
"
spice_ignore=false}
C {devices/code.sym} 345 -565 0 0 {name=s2 only_toplevel=false value="
Expand Down Expand Up @@ -172,5 +172,9 @@ C {devices/lab_wire.sym} 800 -140 0 0 {name=p11 sig_type=std_logic lab=VSSR}
C {devices/vsource.sym} 620 -260 0 0 {name=VDR value=1.8 savecurrent=false}
C {devices/lab_wire.sym} 620 -230 2 1 {name=p25 sig_type=std_logic lab=VSSR}
C {devices/lab_wire.sym} 620 -290 0 0 {name=p26 sig_type=std_logic lab=VDDR}
C {devices/lab_wire.sym} 540 -590 0 0 {name=p27 sig_type=std_logic lab=VDDR}
C {devices/lab_wire.sym} 540 -410 0 0 {name=p28 sig_type=std_logic lab=VSSD}
C {devices/lab_wire.sym} 540 -600 0 0 {name=p27 sig_type=std_logic lab=VDDR}
C {devices/lab_wire.sym} 540 -400 0 0 {name=p28 sig_type=std_logic lab=VSSD}
C {devices/lab_wire.sym} 540 -520 0 0 {name=p29 sig_type=std_logic lab=EN}
C {devices/vsource.sym} 920 -110 0 0 {name=VCLK1 value="PWL(0 0, 10u 0, 10.01u 1.8)" savecurrent=false}
C {devices/lab_wire.sym} 920 -140 0 0 {name=p30 sig_type=std_logic lab=EN}
C {devices/lab_wire.sym} 920 -80 2 1 {name=p31 sig_type=std_logic lab=VSSD}
5 changes: 3 additions & 2 deletions xschem/sar.sch
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ E {}
C {cyclic_flag.sym} 530 -180 0 0 {name=x3}
C {cdac_ctrl.sym} 990 -280 0 0 {name=x4}
C {out_latch.sym} 990 -130 0 0 {name=x5}
C {devices/ipin.sym} 140 -380 0 0 {name=p20 sig_type=std_logic lab=VDDD}
C {devices/ipin.sym} 140 -400 0 0 {name=p20 sig_type=std_logic lab=VDDD}
C {devices/ipin.sym} 140 -300 0 0 {name=p22 sig_type=std_logic lab=VSSD}
C {devices/lab_wire.sym} 380 -320 0 0 {name=p5 sig_type=std_logic lab=VDDD}
C {devices/lab_wire.sym} 380 -210 0 0 {name=p1 sig_type=std_logic lab=VDDD}
Expand Down Expand Up @@ -45,6 +45,7 @@ C {devices/opin.sym} 140 -180 0 0 {name=p52 sig_type=std_logic lab=DOUT[0:9]}
C {devices/opin.sym} 140 -160 0 0 {name=p53 sig_type=std_logic lab=CKO}
C {devices/lab_wire.sym} 680 -300 0 1 {name=p23 sig_type=std_logic lab=CLKSB}
C {devices/opin.sym} 140 -280 0 0 {name=p24 sig_type=std_logic lab=CLKS}
C {devices/lab_wire.sym} 380 -280 0 0 {name=p2 sig_type=std_logic lab=VDDD}
C {devices/lab_wire.sym} 380 -280 0 0 {name=p2 sig_type=std_logic lab=EN}
C {devices/lab_wire.sym} 840 -290 0 0 {name=p6 sig_type=std_logic lab=COMP_N}
C {devices/ipin.sym} 140 -320 0 0 {name=p11 sig_type=std_logic lab=COMP_N}
C {devices/ipin.sym} 140 -380 0 0 {name=p14 sig_type=std_logic lab=EN}
19 changes: 11 additions & 8 deletions xschem/sar.sym
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,18 +12,21 @@ L 4 130 -70 130 70 {}
B 5 -152.5 -62.5 -147.5 -57.5 {name=VDDD sig_type=std_logic dir=in}
L 4 -150 -60 -130 -60 {}
T {VDDD} -125 -64 0 0 0.2 0.2 {}
B 5 -152.5 -42.5 -147.5 -37.5 {name=CLK sig_type=std_logic dir=in}
B 5 -152.5 -42.5 -147.5 -37.5 {name=EN sig_type=std_logic dir=in}
L 4 -150 -40 -130 -40 {}
T {CLK} -125 -44 0 0 0.2 0.2 {}
B 5 -152.5 -22.5 -147.5 -17.5 {name=COMP_P sig_type=std_logic dir=in}
T {EN} -125 -44 0 0 0.2 0.2 {}
B 5 -152.5 -22.5 -147.5 -17.5 {name=CLK sig_type=std_logic dir=in}
L 4 -150 -20 -130 -20 {}
T {COMP_P} -125 -24 0 0 0.2 0.2 {}
B 5 -152.5 -2.5 -147.5 2.5 {name=COMP_N sig_type=std_logic dir=in}
T {CLK} -125 -24 0 0 0.2 0.2 {}
B 5 -152.5 -2.5 -147.5 2.5 {name=COMP_P sig_type=std_logic dir=in}
L 4 -150 0 -130 0 {}
T {COMP_N} -125 -4 0 0 0.2 0.2 {}
B 5 -152.5 17.5 -147.5 22.5 {name=VSSD sig_type=std_logic dir=in}
T {COMP_P} -125 -4 0 0 0.2 0.2 {}
B 5 -152.5 17.5 -147.5 22.5 {name=COMP_N sig_type=std_logic dir=in}
L 4 -150 20 -130 20 {}
T {VSSD} -125 16 0 0 0.2 0.2 {}
T {COMP_N} -125 16 0 0 0.2 0.2 {}
B 5 -152.5 37.5 -147.5 42.5 {name=VSSD sig_type=std_logic dir=in}
L 4 -150 40 -130 40 {}
T {VSSD} -125 36 0 0 0.2 0.2 {}
B 5 147.5 -62.5 152.5 -57.5 {name=CLKS sig_type=std_logic dir=out}
L 4 130 -60 150 -60 {}
T {CLKS} 125 -64 0 1 0.2 0.2 {}
Expand Down

0 comments on commit 005fa2a

Please sign in to comment.