Hardware-AES

Advanced Encryption Standard implemented on hardware level using Verilog HDL.

Name		Name	Last commit message	Last commit date
Latest commit History 34 Commits
.gitignore		.gitignore
AddRoundKey.v		AddRoundKey.v
AddRoundKey2.v		AddRoundKey2.v
InvMixColumns.v		InvMixColumns.v
InvShiftRows.v		InvShiftRows.v
InvSubByte.v		InvSubByte.v
Mul.v		Mul.v
README.md		README.md
RotWord.v		RotWord.v
ShiftRows.v		ShiftRows.v
SubByte.v		SubByte.v
SubWord.v		SubWord.v
decryption.v		decryption.v
eightbitxor.v		eightbitxor.v
encryption.v		encryption.v
firstSim.txt		firstSim.txt
keyexapnsion.do		keyexapnsion.do
keyexpansion.v		keyexpansion.v
mixColumns.v		mixColumns.v
mux2x1.v		mux2x1.v
mux4x1.v		mux4x1.v
secondSim.txt		secondSim.txt
thirdSim.txt		thirdSim.txt
thirtytwobitxor.v		thirtytwobitxor.v
wlft62skt5		wlft62skt5
wlft736t6i		wlft736t6i
wlft8j4017		wlft8j4017
wlft8q1rnc		wlft8q1rnc
wlftaam910		wlftaam910
wlftbcb8eq		wlftbcb8eq
wlftcsnzqa		wlftcsnzqa
wlftd9cmwt		wlftd9cmwt
wlftdcv41n		wlftdcv41n
wlftdcwnyd		wlftdcwnyd
wlftdex340		wlftdex340
wlftetvx1z		wlftetvx1z
wlftgdr9h0		wlftgdr9h0
wlftiyfed5		wlftiyfed5
wlftjeyrk6		wlftjeyrk6
wlftjy5fvx		wlftjy5fvx
wlftk3x1gs		wlftk3x1gs
wlftkbhqi2		wlftkbhqi2
wlftkcq3qj		wlftkcq3qj
wlftnyt3xf		wlftnyt3xf
wlftqk7i2j		wlftqk7i2j
wlftqnyjm5		wlftqnyjm5
wlftr0z8c1		wlftr0z8c1
wlftr3s7f5		wlftr3s7f5
wlftt72c0d		wlftt72c0d
wlftv3tdbj		wlftv3tdbj
wlftwe60yz		wlftwe60yz
wlfty4nhie		wlfty4nhie
wlftycbwac		wlftycbwac
xor32.v		xor32.v
xtime.v		xtime.v

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