RISC-V-in-TL-Verilog

This is a project made to make a RISC-V architecture and know more about TL-verilog. In the future, I am planning to expand it with branch predictions and other techniques used in moder architectures.

Took inspiration and guidance from https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/risc-v_shell.tlv.