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Bus: create a clean slate for new prefetch emulation
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@fleroviux
fleroviux committed Sep 9, 2023
1 parent e0af850 commit fc0360c
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Showing 5 changed files with 68 additions and 62 deletions.
20 changes: 13 additions & 7 deletions src/nba/src/bus/bus.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ void Bus::Reset() {
hw.rcnt[0] = 0;
hw.rcnt[1] = 0;
hw.postflg = 0;
hw.prefetch_buffer_was_disabled = false;
// hw.prefetch_buffer_was_disabled = false;
hw.mgba_log = {};
hw.mgba_log.message.fill(0);
prefetch = {};
Expand Down Expand Up @@ -146,18 +146,24 @@ auto Bus::Read(u32 address, int access) -> T {

if constexpr(std::is_same_v<T, u8>) {
auto shift = ((address & 1) << 3);
Prefetch(address, code, wait16[sequential][page]);
return memory.rom.ReadROM16(address, sequential) >> shift;
// Prefetch(address, code, wait16[sequential][page]);
// return memory.rom.ReadROM16(address, sequential) >> shift;
return ReadGamePakROM16(address, sequential) >> shift;
}

if constexpr(std::is_same_v<T, u16>) {
Prefetch(address, code, wait16[sequential][page]);
return memory.rom.ReadROM16(address, sequential);
// Prefetch(address, code, wait16[sequential][page]);
// return memory.rom.ReadROM16(address, sequential);
return ReadGamePakROM16(address, sequential);
}

if constexpr(std::is_same_v<T, u32>) {
Prefetch(address, code, wait32[sequential][page]);
return memory.rom.ReadROM32(address, sequential);
// Prefetch(address, code, wait32[sequential][page]);
// return memory.rom.ReadROM32(address, sequential);
// @todo: address on the second access should not matter, so why bother adjusting it?
const u32 lsw = ReadGamePakROM16(address, sequential);
const u32 msw = ReadGamePakROM16(address + 2U, true);
return msw << 16 | lsw;
}

return 0;
Expand Down
13 changes: 3 additions & 10 deletions src/nba/src/bus/bus.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,7 @@ struct Bus {
bool cgb = false;
} waitcnt;

bool prefetch_buffer_was_disabled = false;
// bool prefetch_buffer_was_disabled = false;

enum class HaltControl {
Run = 0,
Expand All @@ -109,15 +109,7 @@ struct Bus {
} hw;

struct Prefetch {
bool active = false;
u32 head_address;
u32 last_address;
int count = 0;
int capacity = 8;
int opcode_width = 4;
int countdown;
int duty;
bool thumb;
std::array<u16, 8> buffer{};
} prefetch;

int last_access;
Expand Down Expand Up @@ -247,6 +239,7 @@ struct Bus {

void SIOTransferDone();

u16 ReadGamePakROM16(u32 address, int sequential);
void Prefetch(u32 address, bool code, int cycles);
void StopPrefetch();
void Step(int cycles);
Expand Down
6 changes: 3 additions & 3 deletions src/nba/src/bus/io.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -541,9 +541,9 @@ void Bus::Hardware::WriteByte(u32 address, u8 value) {
waitcnt.ws2[1] = (value >> 2) & 1;
waitcnt.phi = (value >> 3) & 3;
waitcnt.prefetch = (value >> 6) & 1;
if(prefetch_old && !waitcnt.prefetch) {
prefetch_buffer_was_disabled = true;
}
// if(prefetch_old && !waitcnt.prefetch) {
// prefetch_buffer_was_disabled = true;
// }
bus->UpdateWaitStateTable();
break;
}
Expand Down
42 changes: 21 additions & 21 deletions src/nba/src/bus/serialization.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -29,22 +29,22 @@ void Bus::LoadState(SaveState const& state) {
hw.rcnt[0] = state.bus.io.rcnt[0];
hw.rcnt[1] = state.bus.io.rcnt[1];
hw.postflg = state.bus.io.postflg;
hw.prefetch_buffer_was_disabled = state.bus.prefetch_buffer_was_disabled;
// hw.prefetch_buffer_was_disabled = state.bus.prefetch_buffer_was_disabled;

prefetch.active = state.bus.prefetch.active;
prefetch.head_address = state.bus.prefetch.head_address;
prefetch.count = state.bus.prefetch.count;
prefetch.countdown = state.bus.prefetch.countdown;
prefetch.thumb = state.bus.prefetch.thumb;
if(prefetch.thumb) {
prefetch.opcode_width = sizeof(u16);
prefetch.capacity = 8;
prefetch.duty = wait16[int(Access::Sequential)][prefetch.last_address >> 24];
} else {
prefetch.opcode_width = sizeof(u32);
prefetch.capacity = 4;
prefetch.duty = wait32[int(Access::Sequential)][prefetch.last_address >> 24];
}
// prefetch.active = state.bus.prefetch.active;
// prefetch.head_address = state.bus.prefetch.head_address;
// prefetch.count = state.bus.prefetch.count;
// prefetch.countdown = state.bus.prefetch.countdown;
// prefetch.thumb = state.bus.prefetch.thumb;
// if(prefetch.thumb) {
// prefetch.opcode_width = sizeof(u16);
// prefetch.capacity = 8;
// prefetch.duty = wait16[int(Access::Sequential)][prefetch.last_address >> 24];
// } else {
// prefetch.opcode_width = sizeof(u32);
// prefetch.capacity = 4;
// prefetch.duty = wait32[int(Access::Sequential)][prefetch.last_address >> 24];
// }

last_access = state.bus.last_access;

Expand All @@ -70,13 +70,13 @@ void Bus::CopyState(SaveState& state) {
state.bus.io.rcnt[0] = hw.rcnt[0];
state.bus.io.rcnt[1] = hw.rcnt[1];
state.bus.io.postflg = hw.postflg;
state.bus.prefetch_buffer_was_disabled = hw.prefetch_buffer_was_disabled;
// state.bus.prefetch_buffer_was_disabled = hw.prefetch_buffer_was_disabled;

state.bus.prefetch.active = prefetch.active;
state.bus.prefetch.head_address = prefetch.head_address;
state.bus.prefetch.count = prefetch.count;
state.bus.prefetch.countdown = prefetch.countdown;
state.bus.prefetch.thumb = prefetch.thumb;
// state.bus.prefetch.active = prefetch.active;
// state.bus.prefetch.head_address = prefetch.head_address;
// state.bus.prefetch.count = prefetch.count;
// state.bus.prefetch.countdown = prefetch.countdown;
// state.bus.prefetch.thumb = prefetch.thumb;

state.bus.last_access = last_access;

Expand Down
49 changes: 28 additions & 21 deletions src/nba/src/bus/timing.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,9 @@ void Bus::Idle() {
}

void Bus::Prefetch(u32 address, bool code, int cycles) {
if(!code) {
Step(cycles);

/*if(!code) {
StopPrefetch();
Step(cycles);
return;
Expand Down Expand Up @@ -92,34 +94,39 @@ void Bus::Prefetch(u32 address, bool code, int cycles) {
prefetch.countdown = prefetch.duty;
prefetch.last_address = address + prefetch.opcode_width;
prefetch.head_address = prefetch.last_address;
}
}*/
}

void Bus::StopPrefetch() {
if(prefetch.active) {
u32 r15 = hw.cpu.state.r15;

/* If ROM data/SRAM/FLASH is accessed in a cycle, where the prefetch unit
* is active and finishing a half-word access, then a one-cycle penalty applies.
* Note: the prefetch unit is only active when executing code from ROM.
*/
if(r15 >= 0x08000000 && r15 <= 0x0DFFFFFF) {
auto half_duty_plus_one = (prefetch.duty >> 1) + 1;
auto countdown = prefetch.countdown;

if(countdown == 1 || (!prefetch.thumb && countdown == half_duty_plus_one)) {
Step(1);
}
}
// if(prefetch.active) {
// u32 r15 = hw.cpu.state.r15;

// /* If ROM data/SRAM/FLASH is accessed in a cycle, where the prefetch unit
// * is active and finishing a half-word access, then a one-cycle penalty applies.
// * Note: the prefetch unit is only active when executing code from ROM.
// */
// if(r15 >= 0x08000000 && r15 <= 0x0DFFFFFF) {
// auto half_duty_plus_one = (prefetch.duty >> 1) + 1;
// auto countdown = prefetch.countdown;

// if(countdown == 1 || (!prefetch.thumb && countdown == half_duty_plus_one)) {
// Step(1);
// }
// }

// prefetch.active = false;
// }
}

prefetch.active = false;
}
u16 Bus::ReadGamePakROM16(u32 address, int sequential) {
Step(wait16[sequential][address >> 24]);
return memory.rom.ReadROM16(address, sequential);
}

void Bus::Step(int cycles) {
scheduler.AddCycles(cycles);

if(prefetch.active) {
/*if(prefetch.active) {
prefetch.countdown -= cycles;
while(prefetch.countdown <= 0) {
Expand All @@ -132,7 +139,7 @@ void Bus::Step(int cycles) {
break;
}
}
}
}*/
}

void Bus::UpdateWaitStateTable() {
Expand Down

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