SurvivorCore

This repository contains (very) basic processor implementations for the ApocalypseStack in the SystemVerilog HDL. I use Verilator for linting and simulation, and the Yosys synthesis suite, along with several open-source tools to target the Lattice Ice40HX1k FPGA.

Usage

The easiest way to get started is running via Docker, using the provided Dockerfile.

$ make 

Several make targets are provided, the default target above builds a container image. To run the container, compile the processor, and run the tests, use the following targets:

$ make run
$ make test_core 

Waveforms

Verilator provides a C++ interface to dump VCD files tracing interface and internal processor signals for debugging and viewing waveforms (for instance, in a GTK+ viwer). Our tests dump VCD files to the vcds directory at the project level, which can be viewed using:

$ gtkwave vcds/*.vcd &