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Remove lock analysis from stateful transform #735

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merged 3 commits into from
Sep 2, 2024
Merged

Remove lock analysis from stateful transform #735

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a943242
Assigning lock IDS is done in a subsequent pass
newling Sep 2, 2024
2621644
update tests
newling Sep 2, 2024
466654b
Merge branch 'main' into remove_lock_analysis
newling Sep 2, 2024
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64 changes: 8 additions & 56 deletions compiler/plugins/target/AMD-AIE/aie/AMDAIEObjectFifoStatefulTransform.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,6 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

#include <numeric>
#include <set>

#include "AIEDialect.h"
#include "Passes.h"
#include "iree-amd-aie/aie_runtime/iree_aie_runtime.h"
Expand All @@ -15,7 +12,6 @@
#include "mlir/Dialect/MemRef/IR/MemRef.h"
#include "mlir/Dialect/SCF/IR/SCF.h"
#include "mlir/Dialect/SCF/Utils/Utils.h"
#include "mlir/Dialect/Utils/StaticValueUtils.h"
#include "mlir/IR/Attributes.h"
#include "mlir/IR/PatternMatch.h"
#include "mlir/Pass/Pass.h"
Expand All @@ -28,7 +24,6 @@ using namespace mlir::iree_compiler::AMDAIE;
using xilinx::AIE::AIEObjectFifoType;
using xilinx::AIE::BDDimLayoutArrayArrayAttr;
using xilinx::AIE::BDDimLayoutArrayAttr;
using xilinx::AIE::BDDimLayoutAttr;
using xilinx::AIE::BufferOp;
using xilinx::AIE::CoreOp;
using xilinx::AIE::DeviceOp;
Expand Down Expand Up @@ -119,32 +114,6 @@ std::optional<Value> getOptionalSharedTile(ObjectFifoLinkOp op) {

} // namespace

class LockAnalysis {
DenseMap<std::pair<Value, int>, int> locksPerTile;

public:
LockAnalysis(DeviceOp &device) {
for (auto lockOp : device.getOps<LockOp>())
locksPerTile[{lockOp.getTile(), lockOp.getLockID().value()}] = 1;
}

/// Given a tile, returns next usable lockID for that tile.
int getLockID(TileOp &tileOp) {
DeviceOp device = tileOp->getParentOfType<DeviceOp>();
AMDAIEDeviceModel deviceModel =
getDeviceModel(static_cast<AMDAIEDevice>(device.getDevice()));
for (int i = 0;
i < deviceModel.getNumLocks(tileOp.getCol(), tileOp.getRow()); i++) {
std::pair<Value, int> lockId = {tileOp, i};
if (int usageCnt = locksPerTile[lockId]; usageCnt == 0) {
locksPerTile[lockId] = 1;
return i;
}
}
return -1;
}
};

class DMAChannelAnalysis {
DenseMap<Value, uint8_t> producerChannelsPerTile;
DenseMap<Value, uint8_t> consumerChannelsPerTile;
Expand Down Expand Up @@ -721,7 +690,6 @@ void replaceObjectAcquireOp(
void createBuffersAndLocks(
OpBuilder builder, DeviceOp device, ObjectFifoCreateOp createOp,
std::vector<ObjectFifoCreateOp> &splitBecauseLink,
LockAnalysis &lockAnalysis,
DenseMap<ObjectFifoLinkOp, ObjectFifoCreateOp> &objFifoLinks,
DenseMap<ObjectFifoCreateOp, std::vector<BufferOp>> &buffersPerFifo,
DenseMap<ObjectFifoCreateOp, std::vector<LockOp>> &locksPerFifo) {
Expand Down Expand Up @@ -817,31 +785,17 @@ void createBuffersAndLocks(
numElem = 0;

// create corresponding aie2 locks
int prodLockID = lockAnalysis.getLockID(creationTile);
if (prodLockID < 0) {
creationTile->emitOpError("No more locks to allocate!");
assert(prodLockID >= 0);
}
auto prodLock = builder.create<LockOp>(builder.getUnknownLoc(), creationTile,
prodLockID, numElem);
prodLock.getOperation()->setAttr(
SymbolTable::getSymbolAttrName(),
LockOp prodLock = builder.create<LockOp>(
builder.getUnknownLoc(), creationTile, IntegerAttr{},
builder.getI8IntegerAttr(numElem),
builder.getStringAttr(name(createOp).str() + "_prod_lock"));
std::vector<LockOp> locks{prodLock};

int consLockID = lockAnalysis.getLockID(creationTile);
if (consLockID < 0) {
creationTile->emitOpError("No more locks to allocate!");
assert(consLockID >= 0);
}
auto consLock = builder.create<LockOp>(builder.getUnknownLoc(), creationTile,
consLockID, 0);
consLock.getOperation()->setAttr(
SymbolTable::getSymbolAttrName(),
LockOp consLock = builder.create<LockOp>(
builder.getUnknownLoc(), creationTile, IntegerAttr{},
builder.getI8IntegerAttr(0),
builder.getStringAttr(name(createOp).str() + "_cons_lock"));
locks.push_back(consLock);

locksPerFifo[createOp] = locks;
locksPerFifo[createOp] = std::vector<LockOp>{prodLock, consLock};
}

/// Translate ObjectFifoCreateOp ops into routing primitives (Flows) and DMA
Expand Down Expand Up @@ -951,7 +905,6 @@ struct AMDAIEObjectFifoStatefulTransformPass : mlir::OperationPass<DeviceOp> {

void runOnOperation() override {
DeviceOp device = getOperation();
LockAnalysis lockAnalysis(device);
DMAChannelAnalysis dmaAnalysis;
OpBuilder builder = OpBuilder::atBlockEnd(device.getBody());
// maps each objFifo to its corresponding buffer
Expand Down Expand Up @@ -980,8 +933,7 @@ struct AMDAIEObjectFifoStatefulTransformPass : mlir::OperationPass<DeviceOp> {

for (ObjectFifoCreateOp createOp : device.getOps<ObjectFifoCreateOp>())
createBuffersAndLocks(builder, device, createOp, splitBecauseLink,
lockAnalysis, objFifoLinks, buffersPerFifo,
locksPerFifo);
objFifoLinks, buffersPerFifo, locksPerFifo);

// Only the objectFifos we split above require DMA communication; the others
// rely on shared memory and share the same buffers.
Expand Down
8 changes: 4 additions & 4 deletions compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_dma.mlir
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Expand Up @@ -9,12 +9,12 @@
// CHECK: %[[FIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_0"} : memref<i32>
// CHECK: %[[FIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_1"} : memref<i32>
// CHECK: %[[FIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_2"} : memref<i32>
// CHECK: %[[FIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 3 : i8, sym_name = "fifo_cons_prod_lock"}
// CHECK: %[[FIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i8, sym_name = "fifo_cons_cons_lock"}
// CHECK: %[[FIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]]) {init = 3 : i8, sym_name = "fifo_cons_prod_lock"}
// CHECK: %[[FIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]]) {init = 0 : i8, sym_name = "fifo_cons_cons_lock"}
// CHECK: %[[FIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_0"} : memref<i32>
// CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref<i32>
// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "fifo_prod_lock"}
// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"}
// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "fifo_prod_lock"}
// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "fifo_cons_lock"}
// CHECK: %[[BUF83:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf83"} : memref<4xi32>
// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_8_3]], DMA : 0)
// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) {
Expand Down
4 changes: 2 additions & 2 deletions compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l1.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@
// CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref<i32>
// CHECK: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref<i32>
// CHECK: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref<i32>
// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i8, sym_name = "fifo_prod_lock"}
// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"}
// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 4 : i8, sym_name = "fifo_prod_lock"}
// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "fifo_cons_lock"}
// CHECK: %[[BUF23:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "buf23"} : memref<4xi32>
// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) {
// CHECK: %[[C55_I32:.*]] = arith.constant 55 : i32
Expand Down
12 changes: 6 additions & 6 deletions compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l2.mlir
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Expand Up @@ -13,18 +13,18 @@
// CHECK: %[[FIFO1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_1"} : memref<1xi32>
// CHECK: %[[FIFO1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_2"} : memref<1xi32>
// CHECK: %[[FIFO1_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_3"} : memref<1xi32>
// CHECK: %[[FIFO1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 4 : i8, sym_name = "fifo1_cons_prod_lock"}
// CHECK: %[[FIFO1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i8, sym_name = "fifo1_cons_cons_lock"}
// CHECK: %[[FIFO1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]]) {init = 4 : i8, sym_name = "fifo1_cons_prod_lock"}
// CHECK: %[[FIFO1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]]) {init = 0 : i8, sym_name = "fifo1_cons_cons_lock"}
// CHECK: %[[FIFO0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_0"} : memref<1xi32>
// CHECK: %[[FIFO0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_1"} : memref<1xi32>
// CHECK: %[[FIFO0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_2"} : memref<1xi32>
// CHECK: %[[FIFO0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_3"} : memref<1xi32>
// CHECK: %[[FIFO0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 4 : i8, sym_name = "fifo0_cons_prod_lock"}
// CHECK: %[[FIFO0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "fifo0_cons_cons_lock"}
// CHECK: %[[FIFO0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 4 : i8, sym_name = "fifo0_cons_prod_lock"}
// CHECK: %[[FIFO0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 0 : i8, sym_name = "fifo0_cons_cons_lock"}
// CHECK: %[[FIFO0_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo0_buff_0"} : memref<1xi32>
// CHECK: %[[FIFO0_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo0_buff_1"} : memref<1xi32>
// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "fifo0_prod_lock"}
// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo0_cons_lock"}
// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "fifo0_prod_lock"}
// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "fifo0_cons_lock"}
// CHECK: %[[BUF83:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf83"} : memref<1xi32>
// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_1]], DMA : 0)
// CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_8_3]], DMA : 0)
Expand Down
4 changes: 2 additions & 2 deletions compiler/plugins/target/AMD-AIE/aie/test/AIE2_delayed_release.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@
// CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref<i32>
// CHECK: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref<i32>
// CHECK: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref<i32>
// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i8, sym_name = "fifo_prod_lock"}
// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"}
// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 4 : i8, sym_name = "fifo_prod_lock"}
// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "fifo_cons_lock"}
// CHECK: %[[BUF23:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "buf23"} : memref<4xi32>
// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) {
// CHECK: %[[C99_I32:.*]] = arith.constant 99 : i32
Expand Down
4 changes: 2 additions & 2 deletions compiler/plugins/target/AMD-AIE/aie/test/AIE2_static_l1.mlir
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Expand Up @@ -17,8 +17,8 @@
// CHECK-DAG: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref<i32>
// CHECK-DAG: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref<i32>
// CHECK-DAG: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref<i32>
// CHECK-DAG: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i8, sym_name = "fifo_prod_lock"}
// CHECK-DAG: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"}
// CHECK-DAG: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 4 : i8, sym_name = "fifo_prod_lock"}
// CHECK-DAG: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "fifo_cons_lock"}
// CHECK-DAG: %[[DSTBUF22:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "dstbuf22"} : memref<16xi32>
// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) {
// CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32
Expand Down
32 changes: 16 additions & 16 deletions compiler/plugins/target/AMD-AIE/aie/test/allocation_info_test.mlir
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Expand Up @@ -13,30 +13,30 @@
// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0)
// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2)
// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3)
// CHECK: %[[OF_OUT_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 6) {init = 0 : i8, sym_name = "of_out_1_cons_prod_lock"}
// CHECK: %[[OF_OUT_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 7) {init = 0 : i8, sym_name = "of_out_1_cons_cons_lock"}
// CHECK: %[[OF_OUT_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_out_1_cons_prod_lock"}
// CHECK: %[[OF_OUT_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_out_1_cons_cons_lock"}
// CHECK: %[[OF_OUT_1_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_out_1_buff_0"} : memref<64xi16>
// CHECK: %[[OF_OUT_1_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_out_1_buff_1"} : memref<64xi16>
// CHECK: %[[OF_OUT_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 2) {init = 2 : i8, sym_name = "of_out_1_prod_lock"}
// CHECK: %[[OF_OUT_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 3) {init = 0 : i8, sym_name = "of_out_1_cons_lock"}
// CHECK: %[[OF_OUT_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 2 : i8, sym_name = "of_out_1_prod_lock"}
// CHECK: %[[OF_OUT_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 0 : i8, sym_name = "of_out_1_cons_lock"}
// CHECK: %[[OF_IN_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_0"} : memref<64xi16>
// CHECK: %[[OF_IN_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_1"} : memref<64xi16>
// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "of_in_1_cons_prod_lock"}
// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "of_in_1_cons_cons_lock"}
// CHECK: %[[OF_IN_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 4) {init = 0 : i8, sym_name = "of_in_1_prod_lock"}
// CHECK: %[[OF_IN_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 5) {init = 0 : i8, sym_name = "of_in_1_cons_lock"}
// CHECK: %[[OF_OUT_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 2) {init = 0 : i8, sym_name = "of_out_0_cons_prod_lock"}
// CHECK: %[[OF_OUT_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 3) {init = 0 : i8, sym_name = "of_out_0_cons_cons_lock"}
// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 2 : i8, sym_name = "of_in_1_cons_prod_lock"}
// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 0 : i8, sym_name = "of_in_1_cons_cons_lock"}
// CHECK: %[[OF_IN_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_1_prod_lock"}
// CHECK: %[[OF_IN_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_1_cons_lock"}
// CHECK: %[[OF_OUT_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_out_0_cons_prod_lock"}
// CHECK: %[[OF_OUT_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_out_0_cons_cons_lock"}
// CHECK: %[[OF_OUT_0_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_0_buff_0"} : memref<64xi16>
// CHECK: %[[OF_OUT_0_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_0_buff_1"} : memref<64xi16>
// CHECK: %[[OF_OUT_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i8, sym_name = "of_out_0_prod_lock"}
// CHECK: %[[OF_OUT_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i8, sym_name = "of_out_0_cons_lock"}
// CHECK: %[[OF_OUT_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "of_out_0_prod_lock"}
// CHECK: %[[OF_OUT_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "of_out_0_cons_lock"}
// CHECK: %[[OF_IN_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_0"} : memref<64xi16>
// CHECK: %[[OF_IN_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_1"} : memref<64xi16>
// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of_in_0_cons_prod_lock"}
// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of_in_0_cons_cons_lock"}
// CHECK: %[[OF_IN_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "of_in_0_prod_lock"}
// CHECK: %[[OF_IN_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "of_in_0_cons_lock"}
// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "of_in_0_cons_prod_lock"}
// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "of_in_0_cons_cons_lock"}
// CHECK: %[[OF_IN_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_0_prod_lock"}
// CHECK: %[[OF_IN_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_0_cons_lock"}
// CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_2]], DMA : 0)
// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_0]], DMA : 0)
// CHECK: aie.flow(%[[TILE_2_0]], DMA : 1, %[[TILE_2_3]], DMA : 0)
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