[nrf fromlist] drivers: cache: Add barriers to nrf driver #2754
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On Cortex-M33 the access to peripheral registers doesn't act as a data synchronization barrier for memory accesses to normal memory. So before triggering any TASKS for cache operations we need to make sure the core doesn't have any pending memory transactions. Upstream PR #: 88492 Signed-off-by: Karsten Koenig <[email protected]>
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On Cortex-M33 the access to peripheral registers doesn't act as a data synchronization barrier for memory accesses to normal memory. So before triggering any TASKS for cache operations we need to make sure the core doesn't have any pending memory transactions.
Upstream PR #: 88492