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add getRegister function for RegV.
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magiclf committed Aug 30, 2024
1 parent 553f4d3 commit 40ddaa0
Showing 1 changed file with 5 additions and 1 deletion.
Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,11 @@ sealed class InstFmt(val bitSize:Int){
class ImmI(val index:Int, bitSize:Int): InstFmt(bitSize)
class ImmU(val index:Int, bitSize:Int): InstFmt(bitSize)
class ImmF(val index:Int, bitSize:Int): InstFmt(bitSize)
class RegV(val index:Int, bitSize:Int): InstFmt(bitSize)
class RegV(val index:Int, bitSize:Int): InstFmt(bitSize) {
fun getRegister(item:Asm.AsmItem): Int {
return item.opUnits[index].toUnsignedInt()
}
}
class SId( val index:Int, bitSize:Int): InstFmt(bitSize){
fun getString(item:Asm.AsmItem):String {
val value = item.opUnits[index].toUnsignedInt()
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