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vivado xsim xci compatibility. compatible with vivado synthesis.
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skokvermon committed Apr 4, 2023
1 parent 573b1f0 commit c9ed487
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Showing 4 changed files with 103 additions and 33 deletions.
28 changes: 28 additions & 0 deletions edalize/templates/xsim/Makefile.j2
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@@ -0,0 +1,28 @@
#Auto generated by Edalize jinja
include config.mk

all: xsim.dir/$(TARGET)/xsimk

# {{ xci_list}}

{%if xci_list %}
xci.prj: xci.tcl
vivado -mode batch -source xci.tcl
cat $(TARGET).prj >> xci.prj
xsim.dir/$(TARGET)/xsimk: $(SRC_FILES) xci.prj
xelab $(TOPLEVEL) -prj xci.prj -snapshot $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(GEN_PARAMS) $(XELAB_OPTIONS) -debug all
{%else%}
xsim.dir/$(TARGET)/xsimk: $(SRC_FILES)
xelab $(TOPLEVEL) -prj $(TARGET).prj -snapshot $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(GEN_PARAMS) $(XELAB_OPTIONS) -debug all
{%endif%}

run: {{ default_run }}

run-dflt: xsim.dir/$(TARGET)/xsimk
xsim -R $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)

run-vcd: xsim.dir/$(TARGET)/xsimk
xsim -t vcd.tcl $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)

run-gui: xsim.dir/$(TARGET)/xsimk
xsim --gui $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)
12 changes: 12 additions & 0 deletions edalize/templates/xsim/config.mk.j2
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#Auto generated by Edalize
TARGET = {{target}}
TOPLEVEL = {{toplevel}}

VLOG_DEFINES = {{vlog_defines}}
VLOG_INCLUDES = {{vlog_includes}}
GEN_PARAMS = {{gen_params}}

XELAB_OPTIONS = {{xelab_options}}
XSIM_OPTIONS = {{xsim_options}}

SRC_FILES={{" ".join(src_list)}}
13 changes: 13 additions & 0 deletions edalize/templates/xsim/xci.tcl.j2
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@@ -0,0 +1,13 @@
create_project -part {{xci_part}} myProject -force
{% for n in xci_list %}
read_ip {{ n }}
{% endfor %}
generate_target simulation [ get_files *.xci ]
#export_simulation -force -simulator xsim -of_objects [get_files *.xci ]
#get_files -all -of_objects [get_files *.xci]
set f [get_files -compile_order sources -used_in simulation -of [get_files *.xci] -quiet]
set fd [ open "xci.prj" "w" ]
foreach d $f {
puts $fd "verilog work $d"
}
close $fd
83 changes: 50 additions & 33 deletions edalize/xsim.py
Original file line number Diff line number Diff line change
Expand Up @@ -12,42 +12,41 @@


class Xsim(Edatool):
"""
Vivado Xsim backend
* Standard design sources
* IP: Supply the IP core xci file with file_type=xci and other files (like .prj) as file_type=user .
you also have to specify xilinx part number in tools/xsim/part
argtypes = ["plusarg", "vlogdefine", "vlogparam", "generic"]

MAKEFILE_TEMPLATE = """#Auto generated by Edalize
include config.mk
all: xsim.dir/$(TARGET)/xsimk
xsim.dir/$(TARGET)/xsimk:
xelab $(TOPLEVEL) -prj $(TARGET).prj -snapshot $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(GEN_PARAMS) $(XELAB_OPTIONS)
run: xsim.dir/$(TARGET)/xsimk
xsim -R $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)
* you can also set tools/xsim/default_run to "run_vcd" in order to automatically generate vcd file during simulation
"""

run-gui: xsim.dir/$(TARGET)/xsimk
xsim --gui $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)
"""

CONFIG_MK_TEMPLATE = """#Auto generated by Edalize
TARGET = {target}
TOPLEVEL = {toplevel}
argtypes = ["plusarg", "vlogdefine", "vlogparam", "generic"]

VLOG_DEFINES = {vlog_defines}
VLOG_INCLUDES = {vlog_includes}
GEN_PARAMS = {gen_params}

XELAB_OPTIONS = {xelab_options}
XSIM_OPTIONS = {xsim_options}
VCD_TCL = """#tcl script that runs simulation with vcd output
open_vcd xsim_dump.vcd
log_vcd *
run all
close_vcd
quit
"""

@classmethod
def get_doc(cls, api_ver):
if api_ver == 0:
return {
"description": "XSim simulator from the Xilinx Vivado suite",
"members": [
{
"name": "part",
"type": "String",
"desc": "xilinx part if using xci ip",
},
{
"name": "default_run",
"type": "String",
"desc": "default target to run for makefile. use 'run-vcd' for automatic vcd generation",
},
{
"name": "compilation_mode",
"type": "String",
Expand Down Expand Up @@ -81,6 +80,8 @@ def _write_config_files(self):
with open(os.path.join(self.work_root, self.name + ".prj"), "w") as f:
mfcu = []
(src_files, self.incdirs) = self._get_fileset_files()
src_list = []
xci_list = []
for src_file in src_files:
cmd = ""
if src_file.file_type.startswith("verilogSource"):
Expand All @@ -96,10 +97,15 @@ def _write_config_files(self):
cmd = "sv"
elif src_file.file_type in ["user"]:
pass
elif src_file.file_type in ["data"]:
os.system("ln -s %s %s"%(src_file.name, os.path.join(self.work_root, os.path.basename(src_file.name))));
elif src_file.file_type in ["xci"]:
xci_list.append(src_file.name)
else:
_s = "{} has unknown file type '{}'"
logger.warning(_s.format(src_file.name, src_file.file_type))
if cmd:
src_list.append(src_file.name)
if src_file.logical_name:
lib = src_file.logical_name
else:
Expand All @@ -108,7 +114,7 @@ def _write_config_files(self):
if mfc:
f.write("sv work " + " ".join(mfcu))

with open(os.path.join(self.work_root, "config.mk"), "w") as f:
if 1:
vlog_defines = " ".join(
[
"--define {}={}".format(k, self._param_value_str(v))
Expand All @@ -135,20 +141,31 @@ def _write_config_files(self):
xelab_options = " ".join(self.tool_options.get("xelab_options", []))
xsim_options = " ".join(self.tool_options.get("xsim_options", []))

f.write(
self.CONFIG_MK_TEMPLATE.format(
if xci_list:
xci_part = self.tool_options.get("part", "dflt_part")
if xci_part == "dflt_part":
logger.error("When using xci, you must define tools/xsim/part value")
self.render_template("xci.tcl.j2", os.path.join(self.work_root, "xci.tcl"), dict(
xci_list = xci_list,
xci_part = xci_part
))
self.render_template("config.mk.j2", os.path.join(self.work_root, "config.mk"), dict(
target=self.name,
toplevel=self.toplevel,
vlog_defines=vlog_defines,
vlog_includes=vlog_includes,
gen_params=gen_param_args,
xelab_options=xelab_options,
xsim_options=xsim_options,
)
)

with open(os.path.join(self.work_root, "Makefile"), "w") as f:
f.write(self.MAKEFILE_TEMPLATE)
src_list=src_list,
))

self.render_template("Makefile.j2",os.path.join(self.work_root, "Makefile"),dict(
default_run = self.tool_options.get("default_run", "run-dflt"),
xci_list = xci_list
))
with open(os.path.join(self.work_root, "vcd.tcl"), "w") as f:
f.write(self.VCD_TCL)

def run_main(self):
args = ["run"]
Expand Down

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