v1.1.0

core.json

@@ -2,13 +2,13 @@
     "core": {
         "magic": "APF_VER_1",
         "metadata": {
-            "platform_ids": [],
-            "shortname": "template",
-            "description": "Core template. Displays gray test screen.",
+            "platform_ids": ["ex_platform"],
+            "shortname": "Core Template",
+            "description": "APF core template. Displays gray test screen.",
             "author": "Developer",
             "url": "https://github.com/open-fpga/core-template",
-            "version": "1.0",
-            "date_release": "2022-06-30"
+            "version": "1.1.0",
+            "date_release": "2022-08-23"
         },
         "framework": {
             "target_product": "Analogue Pocket",

dist/platforms/ex_platform.json

@@ -0,0 +1,8 @@
+{
+  "platform": {
+    "category": "Example Cores",
+    "name": "Example Platform",
+    "year": 2022,
+    "manufacturer": "Example Manufacturer"
+  }
+}

info.txt

@@ -0,0 +1,3 @@
+Example Core - Core Template
+
+This is a template for a core containing all of the core definition JSON files and FPGA starter code.

src/fpga/ap_core.qsf

@@ -678,12 +678,12 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[21]
 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_tran_pin31
 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_tran_pin30
 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_pin30_pwroff_reset
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to bridge_spimosi
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to bridge_spimiso
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to bridge_1wire
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spimosi
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spimiso
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_1wire
 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to aux_sda
 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to aux_scl
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to bridge_spiclk
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spiclk
 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_de
 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vs
 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[0]
@@ -744,5 +744,5 @@ set_global_assignment -name SDC_FILE core/core_constraints.sdc
 set_global_assignment -name SIGNALTAP_FILE core/stp1.stp
 set_global_assignment -name QIP_FILE core/mf_pllbase.qip
 set_global_assignment -name SIP_FILE core/mf_pllbase.sip
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
+set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

src/fpga/apf/apf_top.v

@@ -8,7 +8,11 @@
 // laws, including, but not limited to, U.S. copyright law. All rights are
 // reserved. By using the APF code you are agreeing to the terms of the End User
 // License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula]
-// and incorporated herein by reference.
+// and incorporated herein by reference. To the extent any use of the APF requires 
+// application of the MIT License or the GNU General Public License and terms of 
+// this APF Software License Agreement and EULA are inconsistent with such license, 
+// the applicable terms of the MIT License or the GNU General Public License, as 
+// applicable, will prevail.
 
 // THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED
 // WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO,
@@ -33,7 +37,7 @@
 // 6515C - Analogue Pocket main unit
 // SOCRATES FPGA
 // 
-// 2022-06-28 Analogue
+// 2022-08-17 Analogue
 
 `default_nettype none
 

src/fpga/apf/build_id.mif

@@ -9,8 +9,8 @@ DATA_RADIX = HEX;
 CONTENT
 BEGIN
 
-   0E0 : 20220712;
-   0E1 : 00223030;
-   0E2 : 01c3abc0;
+   0E0 : 20220823;
+   0E1 : 00024957;
+   0E2 : b7d9142a;
 
 END;

src/fpga/apf/common.v

@@ -8,7 +8,11 @@
 // laws, including, but not limited to, U.S. copyright law. All rights are
 // reserved. By using the APF code you are agreeing to the terms of the End User
 // License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula]
-// and incorporated herein by reference.
+// and incorporated herein by reference. To the extent any use of the APF requires 
+// application of the MIT License or the GNU General Public License and terms of 
+// this APF Software License Agreement and EULA are inconsistent with such license, 
+// the applicable terms of the MIT License or the GNU General Public License, as 
+// applicable, will prevail.
 
 // THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED
 // WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO,

src/fpga/apf/io_bridge_peripheral.v

@@ -8,7 +8,11 @@
 // laws, including, but not limited to, U.S. copyright law. All rights are
 // reserved. By using the APF code you are agreeing to the terms of the End User
 // License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula]
-// and incorporated herein by reference.
+// and incorporated herein by reference. To the extent any use of the APF requires 
+// application of the MIT License or the GNU General Public License and terms of 
+// this APF Software License Agreement and EULA are inconsistent with such license, 
+// the applicable terms of the MIT License or the GNU General Public License, as 
+// applicable, will prevail.
 
 // THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED
 // WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO,
@@ -73,7 +77,7 @@ input   wire            phy_spiss
 synch_3 s00(reset_n, reset_n_s, clk);
 
     wire endian_little_s;
-synch_3 s81(endian_little, endian_little_s, clk);
+synch_3 s01(endian_little, endian_little_s, clk);
 
     wire phy_spiss_s, phy_spiss_r, phy_spiss_f;
 synch_3 s02(phy_spiss, phy_spiss_s, clk, phy_spiss_r, phy_spiss_f);
@@ -89,7 +93,6 @@ synch_3 s02(phy_spiss, phy_spiss_s, clk, phy_spiss_r, phy_spiss_f);
     localparam  ST_WRITE_0      = 'd6;  
     localparam  ST_WRITE_1      = 'd7;  
     localparam  ST_WRITE_2      = 'd8;  
-    localparam  ST_WRITE_3      = 'd9;  
     localparam  ST_ADDR_0       = 'd9;
 
     reg [1:0]   addr_cnt;
@@ -99,8 +102,6 @@ synch_3 s02(phy_spiss, phy_spiss_s, clk, phy_spiss_r, phy_spiss_f);
     // synchronize rd byte flag's rising edge into clk
     wire rx_byte_done_s, rx_byte_done_r;
 synch_3 s03(rx_byte_done, rx_byte_done_s, clk, rx_byte_done_r);
-
-    reg         bursting;
 
     reg [4:0]   spis;
     localparam  ST_SIDLE        = 'd1;
@@ -167,6 +168,7 @@ always @(posedge clk) begin
                 pmp_addr[ 7: 0] <= {rx_byte_2[7:2], 2'b00};
                 // address is latched
                 if( rx_byte_2[0] ) begin
+					data_cnt <= 0;
                     state <= ST_WRITE_0;
                 end else begin
                     data_cnt <= 0;
@@ -320,7 +322,7 @@ always @(posedge phy_spiclk or posedge phy_spiss) begin
         1: begin    rx_dat[5:4] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 2;   end
         2: begin    rx_dat[3:2] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 3;   end
         3: begin 
-            // last bit of the byte
+            // final 2 bits
             rx_byte <= {rx_dat[7:2], phy_spimosi, phy_spimiso};
             rx_latch_idx <= 0;
             rx_byte_done <= 1;

src/fpga/apf/io_pad_controller.v

@@ -8,7 +8,11 @@
 // laws, including, but not limited to, U.S. copyright law. All rights are
 // reserved. By using the APF code you are agreeing to the terms of the End User
 // License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula]
-// and incorporated herein by reference.
+// and incorporated herein by reference. To the extent any use of the APF requires 
+// application of the MIT License or the GNU General Public License and terms of 
+// this APF Software License Agreement and EULA are inconsistent with such license, 
+// the applicable terms of the MIT License or the GNU General Public License, as 
+// applicable, will prevail.
 
 // THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED
 // WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO,
@@ -31,7 +35,7 @@
 // FULLEST EXTENT PERMITTED BY APPLICABLE LAW.
 //
 // pad controller
-// 2020-08-10 Analogue - started
+// 2020-08-17 Analogue
 //
 
 module io_pad_controller (
@@ -136,22 +140,22 @@ always @(posedge clk) begin
         if(rx_word_done) begin
             cnt <= cnt + 1'b1;
             case(cnt)
-            0: cont1_key <= rx_word;
+            0: cont1_key <= rx_word[15:0];
             1: cont1_joy <= rx_word;
-            2: cont1_trig <= rx_word;
+            2: cont1_trig <= rx_word[15:0];
 
-            3: cont2_key <= rx_word;
+            3: cont2_key <= rx_word[15:0];
             4: cont2_joy <= rx_word;
-            5: cont2_trig <= rx_word;
+            5: cont2_trig <= rx_word[15:0];
 
-            6: cont3_key <= rx_word;
+            6: cont3_key <= rx_word[15:0];
             7: cont3_joy <= rx_word;
-            8: cont3_trig <= rx_word;
+            8: cont3_trig <= rx_word[15:0];
 
-            9: cont4_key <= rx_word;
+            9: cont4_key <= rx_word[15:0];
             10: cont4_joy <= rx_word;
             11: begin
-                cont4_trig <= rx_word;
+                cont4_trig <= rx_word[15:0];
                 state <= ST_IDLE;   
             end
             endcase

src/fpga/core/core_bridge_cmd.v

@@ -50,6 +50,8 @@ input   wire    [31:0]  savestate_addr,
 input   wire    [31:0]  savestate_size,
 input   wire    [31:0]  savestate_maxloadsize,
 
+output  reg             osnotify_inmenu,
+
 output  reg             savestate_start,        // core should detect rising edge on this,
 input   wire            savestate_start_ack,    // and then assert ack for at least 1 cycle
 input   wire            savestate_start_busy,   // assert constantly while in progress after ack
@@ -163,6 +165,7 @@ initial begin
     dataslot_allcomplete <= 0;
     savestate_start <= 0;
     savestate_load <= 0;
+    osnotify_inmenu <= 0;
     status_setup_done_queue <= 0;
 end
 
@@ -297,6 +300,7 @@ always @(posedge clk) begin
         end
         16'h0080: begin
             // Data slot request read
+            dataslot_allcomplete <= 0;
             dataslot_requestread <= 1;
             dataslot_requestread_id <= host_20[15:0];
             if(dataslot_requestread_ack) begin
@@ -307,6 +311,7 @@ always @(posedge clk) begin
         end
         16'h0082: begin
             // Data slot request write
+            dataslot_allcomplete <= 0;
             dataslot_requestwrite <= 1;
             dataslot_requestwrite_id <= host_20[15:0];
             if(dataslot_requestwrite_ack) begin
@@ -364,6 +369,11 @@ always @(posedge clk) begin
                 hstate <= ST_DONE_CODE;
             end
         end
+        16'h00B0: begin
+            // OS Notify: Menu State
+            osnotify_inmenu <= host_20[0];
+            hstate <= ST_DONE_OK;
+        end
         default: begin
             hstate <= ST_DONE_ERR;
         end

src/fpga/core/core_top.v

@@ -258,15 +258,66 @@ assign port_tran_sck_dir = 1'b0;    // clock direction can change
 assign port_tran_sd = 1'bz;
 assign port_tran_sd_dir = 1'b0;     // SD is input and not used
 
+// tie off the rest of the pins we are not using
+assign cram0_a = 'h0;
+assign cram0_dq = {16{1'bZ}};
+assign cram0_clk = 0;
+assign cram0_adv_n = 1;
+assign cram0_cre = 0;
+assign cram0_ce0_n = 1;
+assign cram0_ce1_n = 1;
+assign cram0_oe_n = 1;
+assign cram0_we_n = 1;
+assign cram0_ub_n = 1;
+assign cram0_lb_n = 1;
+
+assign cram1_a = 'h0;
+assign cram1_dq = {16{1'bZ}};
+assign cram1_clk = 0;
+assign cram1_adv_n = 1;
+assign cram1_cre = 0;
+assign cram1_ce0_n = 1;
+assign cram1_ce1_n = 1;
+assign cram1_oe_n = 1;
+assign cram1_we_n = 1;
+assign cram1_ub_n = 1;
+assign cram1_lb_n = 1;
+
+assign dram_a = 'h0;
+assign dram_ba = 'h0;
+assign dram_dq = {16{1'bZ}};
+assign dram_dqm = 'h0;
+assign dram_clk = 'h0;
+assign dram_cke = 'h0;
+assign dram_ras_n = 'h1;
+assign dram_cas_n = 'h1;
+assign dram_we_n = 'h1;
+
+assign sram_a = 'h0;
+assign sram_dq = {16{1'bZ}};
+assign sram_oe_n  = 1;
+assign sram_we_n  = 1;
+assign sram_ub_n  = 1;
+assign sram_lb_n  = 1;
+
+assign dbg_tx = 1'bZ;
+assign user1 = 1'bZ;
+assign aux_scl = 1'bZ;
+assign vpll_feed = 1'bZ;
+
 
 // for bridge write data, we just broadcast it to all bus devices
 // for bridge read data, we have to mux it
 // add your own devices here
 always @(*) begin
     casex(bridge_addr)
+    default: begin
+        bridge_rd_data <= 0;
+    end
     32'h10xxxxxx: begin
         // example
         // bridge_rd_data <= example_device_data;
+        bridge_rd_data <= 0;
     end
     32'hF8xxxxxx: begin
         bridge_rd_data <= cmd_bridge_rd_data;
@@ -315,6 +366,8 @@ end
     wire            savestate_load_busy;
     wire            savestate_load_ok;
     wire            savestate_load_err;
+
+    wire            osnotify_inmenu;
 
 // bridge target commands
 // synchronous to clk_74a
@@ -372,6 +425,8 @@ core_bridge_cmd icb (
     .savestate_load_ok      ( savestate_load_ok ),
     .savestate_load_err     ( savestate_load_err ),
 
+    .osnotify_inmenu        ( osnotify_inmenu ),
+
     .datatable_addr         ( datatable_addr ),
     .datatable_wren         ( datatable_wren ),
     .datatable_data         ( datatable_data ),