add support for riscv64 timer

[heyujiao99]

Hi, this patch add support for riscv64 timer,

1. Implemet opal_sys_timer_get_cycles on RISC-V 64 platform using rdtime instruction.
2. Add a method to read tsc frequency on RISC-V 64 platform.
3. Correspondingly modified serveral configuration files.
4. Tested test/util/opal_timer.c on RISC-V hardware,

[root@host util]# ./opal_timer
--> frequency: 50000000 
--> cycle count  
    Slept approximately 50004395 cycles, or 1000087 us 
--> usecs 
    Slept approximately 1000077 us

5. Add RISC-V 64-bit CI test workflow using riscv-gnu-toolchain and qemu-riscv64

[bosilca]

I left few comments, but I can't test this and I don't think our CI run on any risc64.

[bosilca]

This PR is now ready to go. I did not approve it because I don't think we can test it. Do we have a CI or MTT running on risc64 ?

[bwbarrett]

I agree with George that it would be nice to have testing for RISC-V if we're going to add RISC-V support. We do not currently have anything either as a CI hook or nightly tests. @heyujiao99 is this something that your organization might be able to help out with?

Thanks for addressing George's feedback, but it would also be good to squash your commits before we approve / merge.

[heyujiao99]

I agree with George that it would be nice to have testing for RISC-V if we're going to add RISC-V support. We do not currently have anything either as a CI hook or nightly tests. @heyujiao99 is this something that your organization might be able to help out with?

Thanks for addressing George's feedback, but it would also be good to squash your commits before we approve / merge.

I’d be happy to help set up the RISC-V64 test workflow, but I found that GitHub currently only provides Ubuntu images for x86 and ARM. Referring to other projects’ RISC-V testing approaches (e.g., OpenBLAS), using riscv-gnu-toolchain and qemu-riscv64 to compile and test could also work. Would this be an acceptable solution? @bwbarrett @bosilca

[heyujiao99]

This PR is now ready to go. I did not approve it because I don't think we can test it. Do we have a CI or MTT running on risc64 ?

Hello, I‘ve added the RISC-V 64 CI test implementation, could you please help review this code again?