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proper interchange and pipeline
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zero9178 committed Aug 26, 2024
1 parent f4c0d8d commit 5744ed9
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Showing 2 changed files with 6 additions and 5 deletions.
2 changes: 1 addition & 1 deletion codegen/compiler/src/Quidditch/Target/QuidditchTarget.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -191,6 +191,7 @@ class QuidditchTargetBackend final : public IREE::HAL::TargetBackend {
.addPass(quidditch::Snitch::createPromoteOperandsToL1Pass)
.addPass(createCanonicalizerPass)
.addPass(createCSEPass)
.addPass(createLoopInvariantCodeMotionPass)
.addPass(quidditch::Snitch::createPipelineCopyComputePass)
// TODO: Fuse scf.forall after.
.addPass([] {
Expand All @@ -199,7 +200,6 @@ class QuidditchTargetBackend final : public IREE::HAL::TargetBackend {
})
.addPass(createCanonicalizerPass)
.addPass(createCSEPass)
.addPass(createLoopInvariantCodeMotionPass)
.addPass(quidditch::Snitch::createFormMicrokernelsPass);

BufferizationOptions::AllocationFn allocationFn =
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9 changes: 5 additions & 4 deletions codegen/compiler/src/Quidditch/Target/TensorTile.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -139,14 +139,14 @@ applyTileAndFuseToEachRoot(RewriterBase &rewriter,
tilingOptions.setLoopType(scf::SCFTilingOptions::LoopType::ForallOp);
break;
case TilingLevel::L1:
auto loweringConfig =
getLoweringConfig<quidditch::Snitch::LoweringConfigAttr>(
tilingInterfaceOp);
tilingOptions.setTileSizeComputationFunction(
[&](OpBuilder &builder, auto &&...) {
SmallVector<OpFoldResult> result;

SmallVector<int64_t> l1Tiles(
getLoweringConfig<quidditch::Snitch::LoweringConfigAttr>(
tilingInterfaceOp)
.getL1Tiles());
SmallVector<int64_t> l1Tiles(loweringConfig.getL1Tiles());
for (int64_t value : l1Tiles)
result.push_back(builder.getIndexAttr(value));

Expand All @@ -157,6 +157,7 @@ applyTileAndFuseToEachRoot(RewriterBase &rewriter,
return result;
});
tilingOptions.setLoopType(scf::SCFTilingOptions::LoopType::ForOp);
tilingOptions.setInterchange(loweringConfig.getL1TilesInterchange());
break;
}

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