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57 changes: 0 additions & 57 deletions
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codegen/compiler/src/Quidditch/Target/AvoidBankConflicts.cpp
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,147 +1,9 @@ | ||
| #include <memory_decls.h> | ||
| #include <riscv_decls.h> | ||
| #include <ssr_decls.h> | ||
| #include <stdio.h> | ||
| #include <sync_decls.h> | ||
| #include <team_decls.h> | ||
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| #include "/home/markus/CLionProjects/Quidditch/runtime/cmake-build-release/snitch_cluster/cluster_gen/snitch_cluster_addrmap.h" | ||
| #include "/home/markus/CLionProjects/Quidditch/runtime/cmake-build-release/snitch_cluster/cluster_gen/snitch_cluster_peripheral.h" | ||
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| #define CLUSTER_PERF_COUNTER_ADDR \ | ||
| (CLUSTER_PERIPH_BASE_ADDR + \ | ||
| SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_REG_OFFSET) | ||
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| inline uint32_t __attribute__((const)) snrt_cluster_perf_counters_addr() { | ||
| return CLUSTER_PERF_COUNTER_ADDR; | ||
| } | ||
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| #include "/home/markus/CLionProjects/Quidditch/snitch_cluster/sw/snRuntime/src/perf_cnt.h" | ||
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| const unsigned REDUCTION_SIZE = 100; | ||
| const unsigned ROWS = 5; | ||
| const enum snrt_perf_cnt_type METRIC = SNRT_PERF_CNT_TCDM_CONGESTED; | ||
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| // memref<1x161xf64>, memref<5x161xf64>, memref<1x5xf64> | ||
| void kernel161(double vector[], double (*weights)[REDUCTION_SIZE], | ||
| double output[]); | ||
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| // memref<1x100xf64>, memref<5x100xf64>, memref<1x5xf64> | ||
| // In NsNet2 148590 conflicts across 122 streaming regions | ||
| // (1 fill, 120 core computation and 1 elementwise post-processing). | ||
| // Roughly 1217 conflicts per region with one core performing 500 fmadds and | ||
| // 600 memory accesses using the streams. | ||
| // Measured here: 2162. | ||
| void kernel100(double vector[], double (*weights)[REDUCTION_SIZE], | ||
| double output[]); | ||
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| void kernel100_stride112(double vector[], double (*weights)[REDUCTION_SIZE], | ||
| double output[]); | ||
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| unsigned alignTo(unsigned value, unsigned multiple) { | ||
| unsigned int rem = value % multiple; | ||
| if (rem == 0) return value; | ||
| value += multiple - rem; | ||
| return value; | ||
| } | ||
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| double* padToBank(const double* ptr, unsigned bank) { | ||
| bank &= ~1u; | ||
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| size_t address = (size_t)ptr; | ||
| size_t current_bank = (address / 4) % 32; | ||
| if (bank < current_bank) bank += 32; | ||
| address += 4 * (bank - current_bank); | ||
| return (double*)address; | ||
| } | ||
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| void streamerSetup3(); | ||
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| int main() { | ||
| if (snrt_is_dm_core()) { | ||
| snrt_cluster_hw_barrier(); | ||
| snrt_cluster_hw_barrier(); | ||
| snrt_cluster_hw_barrier(); | ||
| snrt_cluster_hw_barrier(); | ||
| return 0; | ||
| } | ||
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| unsigned id = snrt_cluster_core_idx(); | ||
| double* output = (double*)snrt_l1_start_addr() + id * ROWS; | ||
| double* vector = (double*)snrt_l1_start_addr() + 8 * ROWS; | ||
| vector = padToBank(vector, /*bank=*/0); | ||
| double* vector_end = vector + REDUCTION_SIZE; | ||
| vector_end = padToBank(vector_end, 16); | ||
| // for (int i = 0; i < REDUCTION_SIZE; i++) { | ||
| // vector[i] = 1; | ||
| // } | ||
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| // Contiguous layout between the different tiles. | ||
| unsigned dim1Stride = alignTo(REDUCTION_SIZE, 16); | ||
| unsigned dim1Index = id * ROWS; | ||
| double(*weights)[dim1Stride] = | ||
| (double(*)[dim1Stride])(vector_end + dim1Index * dim1Stride); | ||
| // for (int j = 0; j < ROWS; j++) { | ||
| // for (int i = 0; i < REDUCTION_SIZE; i++) { | ||
| // weights[j][i] = id; | ||
| // } | ||
| // } | ||
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| volatile uint32_t* pmtx = snrt_mutex(); | ||
| snrt_mutex_acquire(pmtx); | ||
| if (id == 0) { | ||
| printf("Vector preload will hit banks %d, %d, %d, %d\n", | ||
| (((size_t)vector) / 4) % 32, ((size_t)(vector + 1) / 4) % 32, | ||
| ((size_t)(vector + 2) / 4) % 32, ((size_t)(vector + 3) / 4) % 32); | ||
| } | ||
| printf("Weights[%d] preload will hit banks %d, %d, %d, %d\n", id, | ||
| (((size_t)weights) / 4) % 32, (((size_t)weights[1]) / 4) % 32, | ||
| (((size_t)weights[2]) / 4) % 32, (((size_t)weights[3]) / 4) % 32); | ||
| snrt_mutex_release(pmtx); | ||
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| streamerSetup3(); | ||
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| if (id == 0) { | ||
| snrt_reset_perf_counter(SNRT_PERF_CNT0); | ||
| snrt_start_perf_counter(SNRT_PERF_CNT0, METRIC, 0); | ||
| } | ||
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| // Sync PC. | ||
| uint32_t r; | ||
| asm volatile("csrr %0, mcycle" : "=r"(r) : : "memory"); | ||
| if (id < 8) kernel100(vector, weights, output); | ||
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| snrt_fpu_fence(); | ||
| asm volatile("csrr %0, mcycle" : "=r"(r) : : "memory"); | ||
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| if (id == 0) snrt_stop_perf_counter(SNRT_PERF_CNT0); | ||
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| weights = (double(*)[REDUCTION_SIZE])(((double*)0x1000a5c0) + | ||
| id * 5 * REDUCTION_SIZE); | ||
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| snrt_cluster_hw_barrier(); | ||
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| if (id == 0) printf("%" PRId32 "\n", snrt_get_perf_counter(SNRT_PERF_CNT0)); | ||
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| if (id == 0) { | ||
| snrt_reset_perf_counter(SNRT_PERF_CNT0); | ||
| snrt_start_perf_counter(SNRT_PERF_CNT0, METRIC, 0); | ||
| } | ||
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| // Sync PC. | ||
| asm volatile("csrr %0, mcycle" : "=r"(r) : : "memory"); | ||
| if (id < 8) kernel100(vector, weights, output); | ||
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| snrt_fpu_fence(); | ||
| asm volatile("csrr %0, mcycle" : "=r"(r) : : "memory"); | ||
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| if (id == 0) snrt_stop_perf_counter(SNRT_PERF_CNT0); | ||
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| snrt_cluster_hw_barrier(); | ||
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| // Old: 2118. No bubbles. | ||
| // New: 1931, first time, 2118 second. Bubbles at the start of the first time. | ||
| if (id == 0) printf("%" PRId32 "\n", snrt_get_perf_counter(SNRT_PERF_CNT0)); | ||
| if (!snrt_is_dm_core()) return 0; | ||
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| printf("Hello World\n"); | ||
| return 0; | ||
| } |
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