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add scf_xdsl rule and collect cycles
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3564 |
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module { | ||
func.func public @dsum(%arg0: memref<8x16xf64>, %arg1: memref<8x16xf64>, %arg2: memref<8x16xf64>) -> memref<8x16xf64> { | ||
%c0 = arith.constant 0 : index | ||
%c8 = arith.constant 8 : index | ||
%c1 = arith.constant 1 : index | ||
%c16 = arith.constant 16 : index | ||
scf.for %arg3 = %c0 to %c8 step %c1 { | ||
scf.for %arg4 = %c0 to %c16 step %c1 { | ||
%0 = memref.load %arg0[%arg3, %arg4] : memref<8x16xf64> | ||
%1 = memref.load %arg1[%arg3, %arg4] : memref<8x16xf64> | ||
%2 = arith.addf %0, %1 : f64 | ||
memref.store %2, %arg2[%arg3, %arg4] : memref<8x16xf64> | ||
} | ||
} | ||
return %arg2 : memref<8x16xf64> | ||
} | ||
} |
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@@ -5,3 +5,4 @@ snrt,187 | |
ssr1d,253 | ||
ssr2d,273 | ||
snitch_stream,206 | ||
scf_xdsl,3564 |
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@@ -5,3 +5,4 @@ | |
8x16xf32,ssr1d,253 | ||
8x16xf32,ssr2d,273 | ||
8x16xf32,snitch_stream,206 | ||
8x16xf32,scf_xdsl,3564 |
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2676 |
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module { | ||
func.func public @fill(%arg0: f64, %arg1: memref<16x16xf64>) -> memref<16x16xf64> { | ||
%c0 = arith.constant 0 : index | ||
%c16 = arith.constant 16 : index | ||
%c1 = arith.constant 1 : index | ||
scf.for %arg2 = %c0 to %c16 step %c1 { | ||
scf.for %arg3 = %c0 to %c16 step %c1 { | ||
memref.store %arg0, %arg1[%arg2, %arg3] : memref<16x16xf64> | ||
} | ||
} | ||
return %arg1 : memref<16x16xf64> | ||
} | ||
} |
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@@ -2,3 +2,4 @@ baseline,370 | |
linalg,347 | ||
snitch_stream,296 | ||
snrt,299 | ||
scf_xdsl,2676 |
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|
@@ -2,3 +2,4 @@ | |
16x16xf64,linalg,347 | ||
16x16xf64,snitch_stream,296 | ||
16x16xf64,snrt,299 | ||
16x16xf64,scf_xdsl,2676 |
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21363 |
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module { | ||
func.func public @matmul(%arg0: memref<8x8xf64>, %arg1: memref<8x8xf64>, %arg2: memref<8x8xf64>) -> memref<8x8xf64> { | ||
%c0 = arith.constant 0 : index | ||
%c8 = arith.constant 8 : index | ||
%c1 = arith.constant 1 : index | ||
scf.for %arg3 = %c0 to %c8 step %c1 { | ||
scf.for %arg4 = %c0 to %c8 step %c1 { | ||
scf.for %arg5 = %c0 to %c8 step %c1 { | ||
%0 = memref.load %arg0[%arg3, %arg5] : memref<8x8xf64> | ||
%1 = memref.load %arg1[%arg5, %arg4] : memref<8x8xf64> | ||
%2 = memref.load %arg2[%arg3, %arg4] : memref<8x8xf64> | ||
%3 = arith.mulf %0, %1 : f64 | ||
%4 = arith.addf %2, %3 : f64 | ||
memref.store %4, %arg2[%arg3, %arg4] : memref<8x8xf64> | ||
} | ||
} | ||
} | ||
return %arg2 : memref<8x8xf64> | ||
} | ||
} |
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|
@@ -2,3 +2,4 @@ baseline,4230 | |
linalg,6220 | ||
snitch_stream,2339 | ||
snrt,2321 | ||
scf_xdsl,21363 |
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|
@@ -2,3 +2,4 @@ | |
8x8xf64,linalg,6220 | ||
8x8xf64,snitch_stream,2339 | ||
8x8xf64,snrt,2321 | ||
8x8xf64,scf_xdsl,21363 |
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@@ -1,10 +1,10 @@ | ||
combined,baseline,linalg,linalg_xdsl,snitch_stream,snrt,min_llvm_mlir,speedup | ||
conv2d_d1_s1_3x3 1x8x8x1xf64,1850,3946,,1500,1498,1850,1.23x | ||
dense 8x8xf64,3240,7069,,2721,2711,3240,1.19x | ||
dsum 8x16xf32,1202,1077,194,206,187,1077,5.23x | ||
fill 16x16xf64,370,347,,296,299,347,1.17x | ||
matmul 8x8xf64,4230,6220,,2339,2321,4230,1.81x | ||
pooling_nchw_max_d1_s2_3x3 1x16x16x1xf64,1406,2330,,1116,1124,1406,1.26x | ||
pooling_nchw_sum_d1_s2_3x3 1x16x16x1xf64,1982,3212,,2012,2006,1982,0.99x | ||
relu 16x16xf64,1339,1335,,322,334,1335,4.15x | ||
softmax 16xf64,32611,,,,,32611,?x | ||
combined,baseline,linalg,linalg_xdsl,scf_xdsl,snitch_stream,snrt,min_llvm_mlir,speedup | ||
conv2d_d1_s1_3x3 1x8x8x1xf64,1850,3946,,,1500,1498,1850,1.23x | ||
dense 8x8xf64,3240,7069,,,2721,2711,3240,1.19x | ||
dsum 8x16xf32,1202,1077,194,3564,206,187,1077,5.23x | ||
fill 16x16xf64,370,347,,2676,296,299,347,1.17x | ||
matmul 8x8xf64,4230,6220,,21363,2339,2321,4230,1.81x | ||
pooling_nchw_max_d1_s2_3x3 1x16x16x1xf64,1406,2330,,24729,1116,1124,1406,1.26x | ||
pooling_nchw_sum_d1_s2_3x3 1x16x16x1xf64,1982,3212,,24729,2012,2006,1982,0.99x | ||
relu 16x16xf64,1339,1335,,5020,322,334,1335,4.15x | ||
softmax 16xf64,32611,,,,,,32611,?x |
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24729 |
26 changes: 26 additions & 0 deletions
26
kernels/pooling_nchw_max_d1_s2_3x3/1x16x16x1xf64/scf_xdsl.xdsl.mlir
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module { | ||
func.func public @pooling_nchw_max_d1_s2_3x3(%arg0: memref<1x1x16x16xf64>, %arg1: memref<1x1x7x7xf64>) -> memref<1x1x7x7xf64> { | ||
%c2 = arith.constant 2 : index | ||
%c0 = arith.constant 0 : index | ||
%c1 = arith.constant 1 : index | ||
%c7 = arith.constant 7 : index | ||
%c3 = arith.constant 3 : index | ||
scf.for %arg2 = %c0 to %c7 step %c1 { | ||
scf.for %arg3 = %c0 to %c7 step %c1 { | ||
scf.for %arg4 = %c0 to %c3 step %c1 { | ||
scf.for %arg5 = %c0 to %c3 step %c1 { | ||
%0 = arith.muli %arg2, %c2 : index | ||
%1 = arith.addi %0, %arg4 : index | ||
%2 = arith.muli %arg3, %c2 : index | ||
%3 = arith.addi %2, %arg5 : index | ||
%4 = memref.load %arg0[%c0, %c0, %1, %3] : memref<1x1x16x16xf64> | ||
%5 = memref.load %arg1[%c0, %c0, %arg2, %arg3] : memref<1x1x7x7xf64> | ||
%6 = arith.maxf %5, %4 : f64 | ||
memref.store %6, %arg1[%c0, %c0, %arg2, %arg3] : memref<1x1x7x7xf64> | ||
} | ||
} | ||
} | ||
} | ||
return %arg1 : memref<1x1x7x7xf64> | ||
} | ||
} |
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|
@@ -2,3 +2,4 @@ baseline,1406 | |
linalg,2330 | ||
snitch_stream,1116 | ||
snrt,1124 | ||
scf_xdsl,24729 |
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|
@@ -2,3 +2,4 @@ | |
1x16x16x1xf64,linalg,2330 | ||
1x16x16x1xf64,snitch_stream,1116 | ||
1x16x16x1xf64,snrt,1124 | ||
1x16x16x1xf64,scf_xdsl,24729 |
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@@ -0,0 +1 @@ | ||
24729 |
26 changes: 26 additions & 0 deletions
26
kernels/pooling_nchw_sum_d1_s2_3x3/1x16x16x1xf64/scf_xdsl.xdsl.mlir
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module { | ||
func.func public @pooling_nchw_sum_d1_s2_3x3(%arg0: memref<1x1x16x16xf64>, %arg1: memref<1x1x7x7xf64>) -> memref<1x1x7x7xf64> { | ||
%c2 = arith.constant 2 : index | ||
%c0 = arith.constant 0 : index | ||
%c1 = arith.constant 1 : index | ||
%c7 = arith.constant 7 : index | ||
%c3 = arith.constant 3 : index | ||
scf.for %arg2 = %c0 to %c7 step %c1 { | ||
scf.for %arg3 = %c0 to %c7 step %c1 { | ||
scf.for %arg4 = %c0 to %c3 step %c1 { | ||
scf.for %arg5 = %c0 to %c3 step %c1 { | ||
%0 = arith.muli %arg2, %c2 : index | ||
%1 = arith.addi %0, %arg4 : index | ||
%2 = arith.muli %arg3, %c2 : index | ||
%3 = arith.addi %2, %arg5 : index | ||
%4 = memref.load %arg0[%c0, %c0, %1, %3] : memref<1x1x16x16xf64> | ||
%5 = memref.load %arg1[%c0, %c0, %arg2, %arg3] : memref<1x1x7x7xf64> | ||
%6 = arith.addf %5, %4 : f64 | ||
memref.store %6, %arg1[%c0, %c0, %arg2, %arg3] : memref<1x1x7x7xf64> | ||
} | ||
} | ||
} | ||
} | ||
return %arg1 : memref<1x1x7x7xf64> | ||
} | ||
} |
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|
@@ -2,3 +2,4 @@ baseline,1982 | |
linalg,3212 | ||
snitch_stream,2012 | ||
snrt,2006 | ||
scf_xdsl,24729 |
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|
@@ -2,3 +2,4 @@ | |
1x16x16x1xf64,linalg,3212 | ||
1x16x16x1xf64,snitch_stream,2012 | ||
1x16x16x1xf64,snrt,2006 | ||
1x16x16x1xf64,scf_xdsl,24729 |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1 @@ | ||
5020 |
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@@ -0,0 +1,16 @@ | ||
module { | ||
func.func public @relu(%arg0: memref<16x16xf64>, %arg1: memref<16x16xf64>) -> memref<16x16xf64> { | ||
%c0 = arith.constant 0 : index | ||
%c16 = arith.constant 16 : index | ||
%c1 = arith.constant 1 : index | ||
%cst = arith.constant 0.000000e+00 : f64 | ||
scf.for %arg2 = %c0 to %c16 step %c1 { | ||
scf.for %arg3 = %c0 to %c16 step %c1 { | ||
%0 = memref.load %arg0[%arg2, %arg3] : memref<16x16xf64> | ||
%1 = arith.maxf %0, %cst : f64 | ||
memref.store %1, %arg1[%arg2, %arg3] : memref<16x16xf64> | ||
} | ||
} | ||
return %arg1 : memref<16x16xf64> | ||
} | ||
} |
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|
@@ -4,3 +4,4 @@ ssr_frep,327 | |
snrt,334 | ||
linalg,1335 | ||
snitch_stream,322 | ||
scf_xdsl,5020 |
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|
@@ -4,3 +4,4 @@ | |
16x16xf64,snrt,334 | ||
16x16xf64,linalg,1335 | ||
16x16xf64,snitch_stream,322 | ||
16x16xf64,scf_xdsl,5020 |
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Submodule xdsl
updated
15 files
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@@ -1 +1 @@ | ||
d40ad7beed1fc9e9bb8a2cdbba43545645927f7d | ||
8bddd0aada21c3591a4ab0d325b44116515bf19e |