RISC-V ISA Semantics for Lean

These semantics are generated from the official RISC-V SPEC available at https://github.com/riscv/sail-riscv/.

⚠️ While this repository covers the full RISC-V SPEC, our Lean backend for sail is still work-in-progress. As a result, our semantics are still full of warnings and errors. Similarly, our output is not yet polished for readability.

RISC-V Lean Statistics

Lines: 132174
Definitions: 3531
Inductive definitions: 157
Abbreviations: 127

Warnings and Errors

Errors found: 3
Warnings found: 0

Error Classes

• 1x unknown identifier 'valid_dec_bits'
• 1x unknown identifier 'parse_dec_bits'
• 1x Lean exited with code 1