Queue delay watermark #1920
Merged
Queue delay watermark #1920
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
j-bos
force-pushed
the
delay-watermark
branch
from
90c9470 to
a907e2a
Compare
kcudnik
approved these changes
Nov 6, 2023
srikrishnagopu
approved these changes
Feb 22, 2024
|
You need to squash commits since you changed the name of the enum |
Signed-off-by: Jason Bos <[email protected]>
Done. |
kcudnik
approved these changes
Mar 13, 2024
rlhui
approved these changes
Apr 11, 2024
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Introduce a watermark attribute, SAI_QUEUE_STAT_DELAY_WATERMARK, to report delay experienced for packets per-queue.
At minimum, this should account the longest time a packet was buffered in the queue, so that the reported value will increase during queue congestion.
Implementations are permitted to include additional processing latency in this measurement, depending on the details of the ASIC design and in what stages it generates rx and tx timestamps.