Update ID stage to support ZCMP, ZCMT and CVXIF with Superscalar #2756
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
![github-actions[bot]](https://avatars.githubusercontent.com/in/15368?s=60&v=4){kind=small}
core/commit_stage.sv
Outdated
Comment on lines
305
to
307
| commit_ack_o[1] = 1'b0; | ||
| we_gpr_o[1] = 1'b0; | ||
| wdata_o[1] = commit_instr_i[1].result; |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| commit_ack_o[1] = 1'b0; | |
| we_gpr_o[1] = 1'b0; | |
| wdata_o[1] = commit_instr_i[1].result; | |
| commit_ack_o[1] = 1'b0; | |
| we_gpr_o[1] = 1'b0; | |
| wdata_o[1] = commit_instr_i[1].result; |
core/cvxif_fu.sv
Outdated
Comment on lines
69
to
70
| if (CVA6Cfg.TvalEn) | ||
| x_exception_o.tval = x_off_instr_i; // TODO Optimization : Set exception in IRO. |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| if (CVA6Cfg.TvalEn) | |
| x_exception_o.tval = x_off_instr_i; // TODO Optimization : Set exception in IRO. | |
| if (CVA6Cfg.TvalEn) | |
| x_exception_o.tval = x_off_instr_i; // TODO Optimization : Set exception in IRO. |
core/id_stage.sv
Outdated
| @@ -104,30 +104,52 @@ module id_stage #( | |||
| logic is_ctrl_flow; | |||
| } issue_struct_t; | |||
| issue_struct_t [CVA6Cfg.NrIssuePorts-1:0] issue_n, issue_q; | |||
| // stall required for ZCMP ZCMT CVXIF | |||
| logic [CVA6Cfg.NrIssuePorts-1:0] stall_instr_fetch; | |||
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| logic [CVA6Cfg.NrIssuePorts-1:0] stall_instr_fetch; | |
| logic [CVA6Cfg.NrIssuePorts-1:0] stall_instr_fetch; |
core/id_stage.sv
Outdated
Comment on lines
116
to
120
| logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_rvc; | ||
| logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_rvc; | ||
| logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_rvc; | ||
| logic [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr; | ||
| logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr; |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_rvc; | |
| logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_rvc; | |
| logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_rvc; | |
| logic [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr; | |
| logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr; | |
| logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_rvc; | |
| logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_rvc; | |
| logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_rvc; | |
| logic [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr; | |
| logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr; |
core/id_stage.sv
Outdated
Comment on lines
124
to
127
| logic is_illegal_cvxif_i; | ||
| logic [31:0] instruction_cvxif_i; | ||
| logic is_compressed_cvxif_i; | ||
| logic stall_macro_deco; |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| logic is_illegal_cvxif_i; | |
| logic [31:0] instruction_cvxif_i; | |
| logic is_compressed_cvxif_i; | |
| logic stall_macro_deco; | |
| logic is_illegal_cvxif_i; | |
| logic [ 31:0] instruction_cvxif_i; | |
| logic is_compressed_cvxif_i; | |
| logic stall_macro_deco; |
core/id_stage.sv
Outdated
| issue_n[1] = '{1'b1, decoded_instruction[1], orig_instr[1], is_control_flow_instr[1]}; | ||
| if (fetch_entry_valid_i[1]) begin | ||
| fetch_entry_ready_o[1] = ~stall_instr_fetch[1]; | ||
| issue_n[1] = '{decoded_instruction_valid[1], decoded_instruction[1], orig_instr[1], is_control_flow_instr[1]}; |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| issue_n[1] = '{decoded_instruction_valid[1], decoded_instruction[1], orig_instr[1], is_control_flow_instr[1]}; | |
| issue_n[1] = '{ | |
| decoded_instruction_valid[1], | |
| decoded_instruction[1], | |
| orig_instr[1], | |
| is_control_flow_instr[1] | |
| }; |
core/id_stage.sv
Outdated
| issue_n[1] = '{1'b1, decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]}; | ||
| end else if (fetch_entry_valid_i[0]) begin | ||
| fetch_entry_ready_o[0] = ~stall_instr_fetch[0]; | ||
| issue_n[1] = '{decoded_instruction_valid[0], decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]}; |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| issue_n[1] = '{decoded_instruction_valid[0], decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]}; | |
| issue_n[1] = '{ | |
| decoded_instruction_valid[0], | |
| decoded_instruction[0], | |
| orig_instr[0], | |
| is_control_flow_instr[0] | |
| }; |
core/id_stage.sv
Outdated
| @@ -371,20 +397,20 @@ module id_stage #( | |||
| always_comb begin | |||
| issue_n = issue_q; | |||
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| issue_n = issue_q; | |
| issue_n = issue_q; |
core/id_stage.sv
Outdated
Comment on lines
412
to
413
| fetch_entry_ready_o[0] = ~stall_instr_fetch[0]; | ||
| issue_n[0] = '{decoded_instruction_valid[0], decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]}; |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| fetch_entry_ready_o[0] = ~stall_instr_fetch[0]; | |
| issue_n[0] = '{decoded_instruction_valid[0], decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]}; | |
| fetch_entry_ready_o[0] = ~stall_instr_fetch[0]; | |
| issue_n[0] = '{ | |
| decoded_instruction_valid[0], | |
| decoded_instruction[0], | |
| orig_instr[0], | |
| is_control_flow_instr[0] | |
| }; |
core/id_stage.sv
Outdated
|
|
||
| endmodule |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| endmodule | |
| endmodule |
|
❌ failed run, report available here. |
1 similar comment
|
❌ failed run, report available here. |
|
❌ failed run, report available here. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Add support for Superscalar with ZCMP, ZCMT and CVXIF.
ZCMP decoder, ZCMT decoder and CVXIF interface driver are using port 0.
Standard RVC and 32 bits instruction can take port 0 or 1.