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8347422: Crash during safepoint handler execution with -XX:+UseAPX #23035

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8347422: Crash during safepoint handler execution with -XX:+UseAPX #23035

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8347422: Crash during safepoint handler execution
Jan 10, 2025
be72373
Review comments resolution.
Jan 17, 2025
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32 changes: 26 additions & 6 deletions src/hotspot/cpu/x86/sharedRuntime_x86_64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3020,7 +3020,7 @@ SafepointBlob* SharedRuntime::generate_handler_blob(SharedStubId id, address cal

// Allocate space for the code. Setup code generation tools.
const char* name = SharedRuntime::stub_name(id);
CodeBuffer buffer(name, 2348, 1024);
CodeBuffer buffer(name, 2548, 1024);
MacroAssembler* masm = new MacroAssembler(&buffer);

address start = __ pc();
Expand Down Expand Up @@ -3086,11 +3086,11 @@ SafepointBlob* SharedRuntime::generate_handler_blob(SharedStubId id, address cal
Label bail;
#endif
if (!cause_return) {
Label no_prefix, not_special;
Label no_prefix, not_special, check_rex_prefix;

// If our stashed return pc was modified by the runtime we avoid touching it
__ cmpptr(rbx, Address(rbp, wordSize));
__ jccb(Assembler::notEqual, no_adjust);
__ jcc(Assembler::notEqual, no_adjust);

// Skip over the poll instruction.
// See NativeInstruction::is_safepoint_poll()
Expand All @@ -3113,9 +3113,29 @@ SafepointBlob* SharedRuntime::generate_handler_blob(SharedStubId id, address cal
// 41 85 04 24 test %eax,(%r12)
// 85 45 00 test %eax,0x0(%rbp)
// 41 85 45 00 test %eax,0x0(%r13)

//
// Notes:
// Format of legacy MAP0 test instruction:-
// [REX/REX2] [OPCODE] [ModRM] [SIB] [DISP] [IMM32]
// o For safepoint polling instruction "test %eax,(%rax)", encoding of first register
// operand and base register of memory operand is b/w [0-8), hence we do not require
// additional REX prefix where REX.B bit stores MSB bit of register encoding, which
// is why two bytes encoding is sufficient here.
// o For safepoint polling instruction like "test %eax,(%r8)", register encoding of BASE
// register of memory operand is 1000, thus we need additional REX prefix in this case,
// there by adding additional byte to instruction encoding.
// o In case BASE register is one of the 32 extended GPR registers available only on targets
// supporting Intel APX extension, then we need to emit two bytes REX2 prefix to hold
// most significant two bits of 5 bit register encoding.

if (VM_Version::supports_apx_f()) {
__ cmpb(Address(rbx, 0), Assembler::REX2);
__ jccb(Assembler::notEqual, check_rex_prefix);
__ addptr(rbx, 2);
__ bind(check_rex_prefix);
}
__ cmpb(Address(rbx, 0), NativeTstRegMem::instruction_rex_b_prefix);
__ jcc(Assembler::notEqual, no_prefix);
__ jccb(Assembler::notEqual, no_prefix);
__ addptr(rbx, 1);
__ bind(no_prefix);
#ifdef ASSERT
Expand All @@ -3128,7 +3148,7 @@ SafepointBlob* SharedRuntime::generate_handler_blob(SharedStubId id, address cal
__ andptr(rcx, 0x07); // looking for 0x04 .. 0x05
__ subptr(rcx, 4); // looking for 0x00 .. 0x01
__ cmpptr(rcx, 1);
__ jcc(Assembler::above, not_special);
__ jccb(Assembler::above, not_special);
__ addptr(rbx, 1);
__ bind(not_special);
#ifdef ASSERT
Expand Down