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[RISCV64] Implement CPU plugin just-in-time emitter for Sqrt operation #30675

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@kuanxian1 kuanxian1 commented May 22, 2025

Details:

  • Create fp32 Sqrt operation JIT Emitter for RISCV64 platform with RVV1.0 support
  • Implement JIT Emitter in the JIT Executor
  • Modify RISCV64 kernel to apply developed JIT emitter

Testing:

  • Pass: Verified with QEMU test ../bin/riscv64/Release/ov_cpu_func_tests --gtest_filter="smokeActivationSqrt*"
    image

Related Issue:

#30246

@github-actions github-actions bot added the category: CPU OpenVINO CPU plugin label May 22, 2025
@kuanxian1 kuanxian1 marked this pull request as ready for review May 22, 2025 14:02
@kuanxian1 kuanxian1 requested review from a team as code owners May 22, 2025 14:02
@sys-openvino-ci sys-openvino-ci added the ExternalPR External contributor label May 22, 2025
@a-sidorova a-sidorova self-assigned this May 22, 2025
a-sidorova
a-sidorova previously approved these changes May 22, 2025
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@kuanxian1 changes look good! 👍🏼 Thank you! I left only one comment - please take a look 😊

Comment on lines 851 to 855
case ov::element::i32:
h->vfcvt_f_x_v(dst, src);
h->vfsqrt_v(dst, dst);
h->vfcvt_x_f_v(dst, dst);
break;
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For int32 these conversion instructions will be automatically inserted by JIT Eltwise kernel. It means that if RISC-V RVV doesn't provide int32 instruction for square, we can implement only fp32 support in JIT Emitter for this op.

So may I ask you to please leave only fp32 implementation in JIT emitter impl?

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@kuanxian1 kuanxian1 May 22, 2025

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After I remove the int32 implementation and leave only fp32 implementation, I try to run the test but it's failing on some of the integer activation test. My understanding is that the conversion will be automatically inserted, do you have insights on why this might be happening?
image

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Thank you for letting me know!

It seems that the problem in JIT Kernel for Eltwise ops - when we load/store values and we need to convert f32->i32, we use instruction vfcvt_rtz_x_f_v(...) - conversion to integer value, which round towards zero. Looks like the such conversion rtz is needed only for integer division.

I suggest to do the following steps:

  • Remove i32 implementation from jit_sqrt_emitter
  • Replace vfcvt_rtz_x_f_v(...) with vfcvt_x_f_v(...) in load_vector and store_vector methods in JIT Kernel for conversion f32 -> i32. Please check that now your implementation works correctly for i32 too.
  • Support execution precision i32 in jit_divide_emitter - as far as I remember, RISC-V RVV provide specific instruction for integer division. So I believe that support won't be difficult :)

What do you think about this solution? May I ask you to try this solution please? ☺️

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Looks good to me, I will try this solutions and get back to you with the result. Thanks!

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I pushed the changes, test is passing, can you please review?

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Thanks! Left only one comment :)

@a-sidorova a-sidorova dismissed their stale review May 22, 2025 14:21

Accidentally

@a-sidorova a-sidorova added this to the 2025.3 milestone May 23, 2025
@a-sidorova a-sidorova added the platform: risc-v OpenVINO on RISC-V label May 23, 2025
break;
default:
OV_CPU_JIT_EMITTER_THROW("Unsupported precision");
}
}

std::set<std::vector<element::Type>> jit_divide_emitter::get_supported_precisions(const std::shared_ptr<ov::Node>& node) {
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Could you please add supported precision i32 here?

Comment on lines 851 to 855
case ov::element::i32:
h->vfcvt_f_x_v(dst, src);
h->vfsqrt_v(dst, dst);
h->vfcvt_x_f_v(dst, dst);
break;
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Thanks! Left only one comment :)

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[Good First Issue] [RISCV64]: Implement CPU plugin just-in-time emitter for Sqrt operation
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