{"payload":{"pageCount":4,"repositories":[{"type":"Public","name":"sv-tests","owner":"chipsalliance","isFork":false,"description":"Test suite designed to check compliance with the SystemVerilog standard.","allTopics":["rtl","verilog","systemverilog","hdl","compliance-testing","symbiflow"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":26,"issueCount":45,"starsCount":285,"forksCount":75,"license":"ISC License","participation":[40,21,35,39,36,30,23,33,44,26,36,28,38,34,33,35,48,32,47,40,44,0,23,25,44,46,0,2,0,0,0,0,0,0,0,2,0,0,0,1,1,0,6,0,0,36,33,11,42,52,51,26],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-12T07:23:12.486Z"}},{"type":"Public","name":"synlig","owner":"chipsalliance","isFork":false,"description":"SystemVerilog support for Yosys","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":10,"issueCount":65,"starsCount":154,"forksCount":20,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-12T06:51:22.212Z"}},{"type":"Public","name":"rocket-uncore","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":1,"issueCount":0,"starsCount":3,"forksCount":0,"license":null,"participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-12T01:59:35.523Z"}},{"type":"Public","name":"t1","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":18,"issueCount":16,"starsCount":110,"forksCount":21,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-12T01:29:53.025Z"}},{"type":"Public","name":"dromajo","owner":"chipsalliance","isFork":false,"description":"RISC-V RV64GC emulator designed for RTL co-simulation","allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":6,"issueCount":18,"starsCount":210,"forksCount":63,"license":"Apache License 2.0","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,1,6,0,0,0,0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-11T23:41:08.578Z"}},{"type":"Public","name":"caliptra-rtl","owner":"chipsalliance","isFork":false,"description":"HW Design Collateral for Caliptra RoT IP","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":10,"issueCount":65,"starsCount":63,"forksCount":36,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-11T23:29:49.405Z"}},{"type":"Public","name":"caliptra-sw","owner":"chipsalliance","isFork":false,"description":"Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test","allTopics":[],"primaryLanguage":{"name":"Rust","color":"#dea584"},"pullRequestCount":53,"issueCount":83,"starsCount":50,"forksCount":38,"license":"Apache License 2.0","participation":[41,17,29,23,28,22,17,21,18,24,5,38,21,17,1,1,15,21,17,8,18,8,11,15,16,7,11,17,4,6,5,3,7,0,1,5,9,1,8,4,4,2,3,4,4,2,0,2,1,5,1,1],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-11T21:57:22.913Z"}},{"type":"Public","name":"chisel","owner":"chipsalliance","isFork":false,"description":"Chisel: A Modern Hardware Design Language","allTopics":["chip-generator","chisel","rtl","chisel3","firrtl","scala","verilog"],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":153,"issueCount":307,"starsCount":3908,"forksCount":587,"license":"Apache License 2.0","participation":[9,11,9,6,15,11,5,3,11,7,13,19,8,10,1,2,7,11,26,28,5,7,13,23,16,7,5,7,4,6,15,7,7,11,1,7,9,8,8,9,10,10,16,8,16,7,11,9,15,6,2,6],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-11T17:16:34.988Z"}},{"type":"Public","name":"synlig-logs","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-11T16:10:21.885Z"}},{"type":"Public","name":"chisel-nix","owner":"chipsalliance","isFork":false,"description":"Nix scripts used to manage the chisel projects.","allTopics":[],"primaryLanguage":{"name":"Nix","color":"#7e7eff"},"pullRequestCount":0,"issueCount":0,"starsCount":19,"forksCount":1,"license":null,"participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,16,11,1,14],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-11T10:07:02.255Z"}},{"type":"Public","name":"sv-tests-results","owner":"chipsalliance","isFork":false,"description":"Output of the sv-tests runs.","allTopics":[],"primaryLanguage":{"name":"HTML","color":"#e34c26"},"pullRequestCount":0,"issueCount":0,"starsCount":5,"forksCount":1,"license":null,"participation":[7,4,7,7,8,7,7,7,7,7,7,7,7,7,7,7,8,7,8,7,8,1,3,5,7,6,6,8,6,7,6,7,7,7,5,1,7,7,7,7,8,7,9,5,1,6,9,1,8,7,7,4],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-11T03:06:20.634Z"}},{"type":"Public","name":"Surelog","owner":"chipsalliance","isFork":false,"description":"SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX ","allTopics":["parser","linter","preprocessor","antlr","verilog","python-api","systemverilog","uvm","elaboration","vpi","antlr4-grammar","parser-ast","vpi-api","vpi-standard"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":1,"issueCount":48,"starsCount":352,"forksCount":67,"license":"Apache License 2.0","participation":[20,42,16,11,21,8,11,10,20,0,0,9,19,12,4,0,10,13,0,0,0,2,0,2,0,0,0,0,0,0,0,0,0,1,7,0,0,0,0,0,0,0,0,0,1,0,5,1,0,0,0,2],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-11T02:50:27.707Z"}},{"type":"Public","name":"i3c-core","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":1,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-10T14:30:14.513Z"}},{"type":"Public","name":"Cores-VeeR-EL2","owner":"chipsalliance","isFork":false,"description":"VeeR EL2 Core","allTopics":["fpga","processor","riscv","rtl","risc-v","open-source-hardware","fusesoc","verilator","riscv32","western-digital","axi4","ahb-lite","asic-design","el2"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":8,"issueCount":20,"starsCount":243,"forksCount":73,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-10T14:07:16.002Z"}},{"type":"Public","name":"firrtl-spec","owner":"chipsalliance","isFork":false,"description":"The specification for the FIRRTL language","allTopics":[],"primaryLanguage":{"name":"TeX","color":"#3D6117"},"pullRequestCount":17,"issueCount":23,"starsCount":39,"forksCount":27,"license":null,"participation":[1,3,0,0,0,0,0,21,18,6,1,5,3,1,0,0,0,3,2,1,2,24,6,4,5,0,3,2,2,1,3,2,2,0,0,3,0,0,1,0,0,4,0,2,1,1,2,5,2,1,2,2],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-10T02:45:36.748Z"}},{"type":"Public","name":"rocket-chip","owner":"chipsalliance","isFork":false,"description":"Rocket Chip Generator","allTopics":["chisel","scala","rocket-chip","chip-generator","riscv","rtl"],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":61,"issueCount":224,"starsCount":3156,"forksCount":1112,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-09T21:12:50.490Z"}},{"type":"Public","name":"VeeR-EL2-Tock","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Rust","color":"#dea584"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-09T11:24:44.595Z"}},{"type":"Public","name":"rvdecoderdb","owner":"chipsalliance","isFork":false,"description":"The Scala parser to parse riscv/riscv-opcodes generate","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":1,"issueCount":0,"starsCount":5,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-09T10:25:21.682Z"}},{"type":"Public","name":"idealchisel","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-07T17:41:27.499Z"}},{"type":"Public","name":"firtool-resolver","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-06T19:39:45.646Z"}},{"type":"Public","name":"caliptra-ss","owner":"chipsalliance","isFork":false,"description":"HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.","allTopics":["security","rot","ocp","root-of-trust","caliptra","opencomputeproject"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":11,"starsCount":2,"forksCount":0,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-06T18:57:46.285Z"}},{"type":"Public","name":"chips-alliance-website","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SCSS","color":"#c6538c"},"pullRequestCount":2,"issueCount":9,"starsCount":3,"forksCount":3,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-05T23:26:55.080Z"}},{"type":"Public","name":"tac","owner":"chipsalliance","isFork":false,"description":"CHIPS Alliance Technical Advisory Council","allTopics":[],"primaryLanguage":null,"pullRequestCount":1,"issueCount":19,"starsCount":5,"forksCount":22,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-05T23:24:15.207Z"}},{"type":"Public","name":"Caliptra","owner":"chipsalliance","isFork":false,"description":"Caliptra IP and firmware for integrated Root of Trust block","allTopics":[],"primaryLanguage":null,"pullRequestCount":2,"issueCount":16,"starsCount":116,"forksCount":29,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-05T15:51:55.162Z"}},{"type":"Public","name":"chisel-interface","owner":"chipsalliance","isFork":false,"description":"The 'missing header' for Chisel","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":0,"starsCount":15,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-02T15:02:44.177Z"}},{"type":"Public","name":"amba","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-30T03:21:23.908Z"}},{"type":"Public","name":"caliptra-dpe","owner":"chipsalliance","isFork":false,"description":"High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs","allTopics":[],"primaryLanguage":{"name":"Rust","color":"#dea584"},"pullRequestCount":5,"issueCount":9,"starsCount":16,"forksCount":20,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-29T23:53:43.938Z"}},{"type":"Public","name":"riscv-dv","owner":"chipsalliance","isFork":false,"description":"Random instruction generator for RISC-V processor verification","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":16,"issueCount":112,"starsCount":997,"forksCount":323,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-29T08:33:41.695Z"}},{"type":"Public","name":"VeeRwolf","owner":"chipsalliance","isFork":false,"description":"FuseSoC-based SoC for VeeR EH1 and EL2","allTopics":["tools","fusesoc","swerv","veer"],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":21,"starsCount":277,"forksCount":64,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-24T21:34:08.458Z"}},{"type":"Public","name":"verible","owner":"chipsalliance","isFork":false,"description":"Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server","allTopics":["productivity","analysis","style-linter","language-server-protocol","syntax-tree","lexer","yacc","systemverilog","hacktoberfest","lsp-server","systemverilog-parser","systemverilog-developer","sv-lrm","verible","parser","formatter","linter"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":29,"issueCount":465,"starsCount":1310,"forksCount":200,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-24T04:06:27.936Z"}}],"repositoryCount":107,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"chipsalliance repositories"}