fix: WriteAction for system register #86

parsa-epfl · Nov 28, 2024 · 3f26e83 · 3f26e83
1 parent 75d8e96
commit 3f26e83
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Showing 2 changed files with 41 additions and 39 deletions.
diff --git a/components/Decoder/Effects.cpp b/components/Decoder/Effects.cpp
@@ -4,6 +4,7 @@
 #include "components/uArch/systemRegister.hpp"
 #include "components/uArch/uArchInterfaces.hpp"
 #include "components/uFetch/uFetchTypes.hpp"
+#include "core/debug/debug.hpp"
 
 #include <core/performance/profile.hpp>
 
@@ -1082,42 +1083,42 @@ readPR(SemanticInstruction* inst, ePrivRegs aPR, std::unique_ptr<SysRegInfo> ri)
     inst->addNewComponent(e);
     return e;
 }
-//
-// struct WritePREffect : public Effect {
-//  ePrivRegs thePR;
-//  std::unique_ptr<SysRegInfo> ri;
-//  WritePREffect(ePrivRegs aPR, std::unique_ptr<SysRegInfo> anRI) : thePR(aPR), ri(std::move(anRI)) {
-//  }
-//
-//  void invoke(SemanticInstruction &anInstruction) {
-//    FLEXUS_PROFILE();
-//    if (!anInstruction.isAnnulled()) {
-//      uint64_t rs = 0;
-//      if (anInstruction.hasOperand(kResult)) {
-//        rs = anInstruction.operand<uint64_t>(kResult);
-//      } else if (anInstruction.hasOperand(kResult1)) {
-//        rs = anInstruction.operand<uint64_t>(kResult1);
-//      }
-//      DBG_(Iface,
-//           (<< anInstruction << " Write " << ri->name << " value= " << std::hex << rs << std::dec));
-//
-//      ri->writefn(anInstruction.core(), (uint64_t)rs);
-//    }
-//    Effect::invoke(anInstruction);
-//  }
-//
-//  void describe(std::ostream &anOstream) const {
-//    anOstream << " Write PR " << thePR;
-//    Effect::describe(anOstream);
-//  }
-//};
-//
-// Effect *writePR(SemanticInstruction *inst, ePrivRegs aPR, std::unique_ptr<SysRegInfo> anRI) {
-//  WritePREffect *e = new WritePREffect(aPR, std::move(anRI));
-//  inst->addNewComponent(e);
-//  return e;
-//}
-//
+
+struct WritePREffect : public Effect {
+ ePrivRegs thePR;
+ std::unique_ptr<SysRegInfo> ri;
+ WritePREffect(ePrivRegs aPR, std::unique_ptr<SysRegInfo> anRI) : thePR(aPR), ri(std::move(anRI)) {
+ }
+
+ void invoke(SemanticInstruction &anInstruction) {
+   FLEXUS_PROFILE();
+   if (!anInstruction.isAnnulled()) {
+     uint64_t rs = 0;
+     if (anInstruction.hasOperand(kResult)) {
+       rs = anInstruction.operand<uint64_t>(kResult);
+     } else if (anInstruction.hasOperand(kResult1)) {
+       rs = anInstruction.operand<uint64_t>(kResult1);
+     }
+     DBG_(Iface,
+          (<< anInstruction << " Write " << ri->name << " value= " << std::hex << rs << std::dec));
+
+     ri->writefn(anInstruction.core(), (uint64_t)rs);
+   }
+   Effect::invoke(anInstruction);
+ }
+
+ void describe(std::ostream &anOstream) const {
+   anOstream << " Write PR " << thePR;
+   Effect::describe(anOstream);
+ }
+};
+
+Effect *writePR(SemanticInstruction *inst, ePrivRegs aPR, std::unique_ptr<SysRegInfo> anRI) {
+ WritePREffect *e = new WritePREffect(aPR, std::move(anRI));
+ inst->addNewComponent(e);
+ return e;
+}
+
 struct WritePSTATE : public Effect {
  uint8_t theOp1, theOp2;
  WritePSTATE(uint8_t anOp1, uint8_t anOp2) : theOp1(anOp1), theOp2(anOp2) {
@@ -1145,7 +1146,7 @@ struct WritePSTATE : public Effect {
        anInstruction.core()->setDAIF((uint32_t)val | anInstruction.core()->_PSTATE().DAIF());
        break;
      case 0x1f: // daif clr
-       anInstruction.core()->setDAIF((uint32_t)val ^ anInstruction.core()->_PSTATE().DAIF());
+       anInstruction.core()->setDAIF((uint32_t)(~val & anInstruction.core()->_PSTATE().DAIF()));
        break;
      default:
        anInstruction.setWillRaise(kException_UNCATEGORIZED);

diff --git a/components/Decoder/encodings/Branch.cpp b/components/Decoder/encodings/Branch.cpp
@@ -4,6 +4,7 @@
 #include "../Effects.hpp"
 #include "Unallocated.hpp"
 #include "components/Decoder/Conditions.hpp"
+#include "components/Decoder/OperandCode.hpp"
 #include "components/Decoder/SemanticActions.hpp"
 #include "components/uArch/systemRegister.hpp"
 
@@ -499,14 +500,14 @@ SYS(archcode const& aFetchedOpcode, uint32_t aCPU, int64_t aSequenceNo)
         inst->addPostvalidation(validateXRegister(rt, kResult, inst, true));
     } else {
         inst->setClass(clsComputation, codeWRPR);
-        return inst; // FIXME: This will never actually write the register
 
         std::vector<std::list<InternalDependance>> rs_dep(1);
         // need to halt dispatch for writes
         inst->setHaltDispatch();
         inst->addCheckTrapEffect(checkSystemAccess(inst, op0, op1, op2, crn, crm, rt, l));
+        predicated_action exec = addExecute(inst, (operation(kMOV_)), {kOperand1}, rs_dep, kResult);
         addReadXRegister(inst, 1, rt, rs_dep[0], true);
-        addExecute(inst, operation(kMOV_), rs_dep);
+        connectDependance(inst->retirementDependance(), exec);
         std::unique_ptr<SysRegInfo> ri = getPriv(op0, op1, op2, crn, crm);
         ri->setSystemRegisterEncodingValues(op0, op1, op2, crn, crm);
         inst->addRetirementEffect(writePR(inst, pr, std::move(ri)));