added missing read/write functions for the missing sysregs

parsa-epfl · Aug 16, 2024 · 47e82ee · 47e82ee
1 parent 0607771
commit 47e82ee
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Showing 4 changed files with 74 additions and 8 deletions.
diff --git a/components/uArch/CoreModel/construct.cpp b/components/uArch/CoreModel/construct.cpp
@@ -493,6 +493,18 @@ CoreImpl::getSP_el(uint8_t anId)
     DBG_Assert(anId >= 0 || anId < 4);
     return theSP_el[anId];
 }
+void
+CoreImpl::setSPSR_el(uint8_t anId, uint64_t aVal)
+{
+    DBG_Assert(anId >= 0 || anId < 4);
+    theSPSR_EL[anId] = aVal;
+}
+uint64_t
+CoreImpl::getSPSR_el(uint8_t anId)
+{
+    DBG_Assert(anId >= 0 || anId < 4);
+    return theSPSR_EL[anId];
+}
 uint32_t
 CoreImpl::getPSTATE()
 {
@@ -585,6 +597,16 @@ CoreImpl::setDAIF(uint32_t aDAIF)
     thePSTATE = ((thePSTATE & ~PSTATE_DAIF) | (aDAIF & PSTATE_DAIF));
 }
 void
+CoreImpl::setELR_el(uint8_t anEL, uint64_t aVal)
+{
+    theELR_EL[anEL] = aVal;
+}
+uint64_t
+CoreImpl::getELR_el(uint8_t anEL)
+{
+    return theELR_EL[anEL];
+}
+void
 CoreImpl::setPC(uint64_t aPC)
 {
     thePC = aPC;

diff --git a/components/uArch/CoreModel/coreModelImpl.hpp b/components/uArch/CoreModel/coreModelImpl.hpp
@@ -161,6 +161,8 @@ class CoreImpl : public CoreModel {
   std::map<VirtualMemoryAddress, uint64_t> theLocalExclusiveVirtualMonitor;
 
   uint64_t theSP_el[4];
+  uint64_t theELR_EL[4];
+  uint64_t theSPSR_EL[4];
 
   eExceptionType thePendingTrap;
   boost::intrusive_ptr<Instruction> theTrapInstruction;
@@ -732,6 +734,10 @@ class CoreImpl : public CoreModel {
   void setXRegister(uint32_t aReg, uint64_t aVal);
   uint64_t getXRegister(uint32_t aReg);
   void setPC(uint64_t aPC);
+  void setELR_el(uint8_t anEL, uint64_t aVal);
+  uint64_t getELR_el(uint8_t anEL);
+  void setSPSR_el(uint8_t anEL, uint64_t aVal);
+  uint64_t getSPSR_el(uint8_t anEL);
   void setDAIF(uint32_t aDAIF);
 
   /* Msutherl: API to read system register value using QEMU encoding */

diff --git a/components/uArch/systemRegister.cpp b/components/uArch/systemRegister.cpp
@@ -80,6 +80,11 @@ class NZCV_ : public SysRegInfo
 
     } // FIXME
     virtual uint64_t readfn(uArch* aCore) override { return aCore->_PSTATE().NZCV(); }
+    virtual void sync(uArch* aCore, size_t theNode) override
+    {
+        auto pstate = Flexus::Qemu::API::qemu_api.read_register(theNode, Flexus::Qemu::API::PSTATE, 0);
+        writefn(aCore, extract32(pstate, 28, 4));
+    }
 
     NZCV_()
       : SysRegInfo("NZCV_",
@@ -117,6 +122,11 @@ class DAIF_ : public SysRegInfo
     virtual void writefn(uArch* aCore, uint64_t aVal) override { aCore->setDAIF(aVal); } // FIXME
     virtual void reset(uArch* aCore) override { DBG_Assert(false); } // FIXME /*arm_cp_reset_ignore*/
     virtual uint64_t readfn(uArch* aCore) override { return aCore->_PSTATE().DAIF(); }
+    virtual void sync(uArch* aCore, size_t theNode) override
+    {
+        auto pstate = Flexus::Qemu::API::qemu_api.read_register(theNode, Flexus::Qemu::API::PSTATE, 0);
+        writefn(aCore, pstate);
+    }
     DAIF_()
       : SysRegInfo("DAIF_",
                    DAIF_::state,
@@ -259,6 +269,8 @@ class DCZID_EL0_ : public SysRegInfo
     uint64_t resetvalue                   = -1;
 
     virtual uint64_t readfn(uArch* aCore) override { return aCore->readDCZID_EL0(); }
+    // No need for sync, effects are done by the readfn
+    virtual void sync(uArch* aCore, size_t theNode) override {}
     DCZID_EL0_()
       : SysRegInfo("DCZID_EL0_",
                    DCZID_EL0_::state,
@@ -287,6 +299,8 @@ class DC_ZVA_ : public SysRegInfo
     static const eRegInfo type            = kARM_DC_ZVA;
     uint64_t resetvalue                   = -1;
     virtual eAccessResult accessfn(uArch* aCore) override { return aCore->accessZVA(); }
+    // No need for sync, effects are done by the readfn
+    virtual void sync(uArch* aCore, size_t theNode) override {}
     DC_ZVA_()
       : SysRegInfo("DC_ZVA_",
                    DC_ZVA_::state,
@@ -315,6 +329,17 @@ class CURRENT_EL_ : public SysRegInfo
     static const eRegInfo type            = kARM_CURRENTEL;
     uint64_t resetvalue                   = -1;
 
+    virtual uint64_t readfn(uArch* aCore) override { return aCore->_PSTATE().EL(); }
+    virtual void writefn(uArch* aCore, uint64_t aVal) override
+    {
+        aCore->setPSTATE(deposit32(aCore->_PSTATE().d(), 2, 2, aVal));
+    }
+    virtual void sync(uArch* aCore, size_t theNode) override
+    {
+        auto pstate = Flexus::Qemu::API::qemu_api.read_register(theNode, Flexus::Qemu::API::PSTATE, 0);
+        writefn(aCore, extract32(pstate, 2, 2));
+    }
+
     CURRENT_EL_()
       : SysRegInfo("CURRENT_EL_",
                    CURRENT_EL_::state,
@@ -341,6 +366,9 @@ class ELR_EL1_ : public SysRegInfo
     static const eAccessRight access      = kPL1_RW;
     static const eRegInfo type            = kARM_ALIAS;
 
+    virtual uint64_t readfn(uArch* aCore) override { return aCore->getELR_el(1); }
+    virtual void writefn(uArch* aCore, uint64_t aVal) override { aCore->setELR_el(1, aVal); }
+
     ELR_EL1_()
       : SysRegInfo("ELR_EL1",
                    ELR_EL1_::state,
@@ -368,7 +396,8 @@ class SPSR_EL1_ : public SysRegInfo
     static const eRegInfo type            = kARM_ALIAS;
     uint64_t resetvalue                   = -1;
 
-    virtual uint64_t readfn(uArch* aCore) override { return aCore->getSP_el(1); }
+    virtual uint64_t readfn(uArch* aCore) override { return aCore->getSPSR_el(1); }
+    virtual void writefn(uArch* aCore, uint64_t aVal) override { return aCore->setSPSR_el(1, aVal); }
 
     SPSR_EL1_()
       : SysRegInfo("SPSR_EL1",
@@ -471,14 +500,11 @@ class SPSel_ : public SysRegInfo
     uint64_t resetvalue                   = -1;
 
     /*spsel_read*/
-    virtual uint64_t readfn(uArch* aCore) override
-    {
-        unsigned int cur_el = aCore->_PSTATE().EL();
-        return aCore->getSP_el(cur_el);
-    }
+    virtual uint64_t readfn(uArch* aCore) override { return aCore->_PSTATE().SP(); }
     virtual void writefn(uArch* aCore, uint64_t aVal) override
     {
-        unsigned int cur_el = aCore->_PSTATE().EL();
+        aCore->setPSTATE(deposit32(aCore->_PSTATE().d(), 0, 1, aVal));
+        // unsigned int cur_el = aCore->_PSTATE().EL();
         /* Update PSTATE SPSel bit; this requires us to update the
          * working stack pointer in xregs[31].
          */
@@ -505,7 +531,7 @@ class SPSel_ : public SysRegInfo
         //            aCore->setXRegister(31, aCore->getSP_el(0));
         //        }
 
-        aCore->setSP_el(cur_el, aVal);
+        // aCore->setSP_el(cur_el, aVal);
     }
 
     SPSel_()

diff --git a/components/uArch/uArchInterfaces.hpp b/components/uArch/uArchInterfaces.hpp
@@ -902,6 +902,12 @@ struct uArch
         DBG_Assert(false);
         return 0;
     }
+    virtual void setSPSR_el(uint8_t anEL, uint64_t aVal) { DBG_Assert(false); }
+    virtual uint64_t getSPSR_el(uint8_t anEL)
+    {
+        DBG_Assert(false);
+        return 0;
+    }
     virtual void setSPSel(uint32_t aVal) { DBG_Assert(false); }
     virtual uint32_t getSPSel()
     {
@@ -949,6 +955,12 @@ struct uArch
         DBG_Assert(false);
         return 0;
     }
+    virtual void setELR_el(uint8_t anEL, uint64_t aVal) { DBG_Assert(false); }
+    virtual uint64_t getELR_el(uint8_t anEL)
+    {
+        DBG_Assert(false);
+        return 0;
+    }
     virtual void setHCREL2(uint64_t aSCTLR) { DBG_Assert(false); }
     virtual uint64_t getHCREL2()
     {