fix: remove EL2 support

Setting virtualization=on in QEMU makes the kernel and the userspace program uses EL2 mode. This makes the address translation complicated. EL2 was never properly supported by other components either. Removing it makes the design simple and clear. Co-authored-by: Bryan Perdrizat <[email protected]>
parsa-epfl · Sep 30, 2024 · 502e947 · 502e947
1 parent 1d4aef7
commit 502e947
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Showing 5 changed files with 43 additions and 239 deletions.
diff --git a/components/MMU/MMUUtil.cpp b/components/MMU/MMUUtil.cpp
@@ -38,22 +38,17 @@ TTEDescriptor::isBlockEntry()
 }
 
 void
-fm_print_mmu_regs(mmu_regs_t* r)
+fm_print_mmu_regs(mmu_regs_t* mmu_regs)
 {
-    DBG_(VVerb,
-         (<< "SCTLR_EL1: " << std::hex << r->SCTLR[EL1] << std::dec << std::endl
-          << "SCTLR_EL2: " << std::hex << r->SCTLR[EL2] << std::dec << std::endl
-          << "SCTLR_EL3: " << std::hex << r->SCTLR[EL3] << std::dec << std::endl
-          << "TCR_EL1: " << std::hex << r->TCR[EL1] << std::dec << std::endl
-          << "TCR_EL2: " << std::hex << r->TCR[EL2] << std::dec << std::endl
-          << "TCR_EL3: " << std::hex << r->TCR[EL3] << std::dec << std::endl
-          << "TTBR0_EL1: " << std::hex << r->TTBR0[EL1] << std::dec << std::endl
-          << "TTBR1_EL1: " << std::hex << r->TTBR1[EL1] << std::dec << std::endl
-          << "TTBR0_EL2: " << std::hex << r->TTBR0[EL2] << std::dec << std::endl
-          << "TTBR1_EL2: " << std::hex << r->TTBR1[EL2] << std::dec << std::endl
-          << "TTBR0_EL3: " << std::hex << r->TTBR0[EL3] << std::dec << std::endl
-          << "ID_AA64MMFR0_EL1: " << std::hex << r->ID_AA64MMFR0_EL1 << std::dec));
-    ;
+    DBG_(VVerb, (<< "Initializing mmu registers from QEMU..." << std::endl
+                    << std::hex
+                    << "\t" << "TCR_EL1: " << mmu_regs->TCR[EL1] << std::endl
+                    << "\t" << "SCTLR_El1: " << mmu_regs->SCTLR[EL1] << std::endl
+                    << "\t" << "TTBR0_EL1: " << mmu_regs->TTBR0[EL1] << std::endl
+                    << "\t" << "TTBR1_EL1: " << mmu_regs->TTBR1[EL1] << std::endl
+                    << "\t" << "ID_AA64MMFR0_EL1: " << mmu_regs->ID_AA64MMFR0_EL1
+                    << std::dec
+                    << std::endl));
 }
 void
 mmu_t::setupBitConfigs()
@@ -112,39 +107,31 @@ mmu_t::init_mmu_regs(std::size_t core_index)
     /**
      * Everything here is detailed in the chapter D7
      * of the 2024 ARM Reference manual. (ARM DDI 0487K.a)
+     *
+     * Bryan Perdrizat
+     *      EL2 and EL3 are not setted up because QFlex is not (yet)
+     *      supporting well EL2 (hypervisor) mode well.
      */
 
     //? sctlr_el0 does not exist
     mmu_regs.SCTLR[EL1] = cpu.read_register(Qemu::API::SCTLR, EL1);
-    mmu_regs.SCTLR[EL2] = cpu.read_register(Qemu::API::SCTLR, EL2);
-    mmu_regs.SCTLR[EL3] = cpu.read_register(Qemu::API::SCTLR, EL3);
 
     //? tcr_el0 does not exist
     mmu_regs.TCR[EL1] = cpu.read_register(Qemu::API::TCR, EL1);
-    mmu_regs.TCR[EL2] = cpu.read_register(Qemu::API::TCR, EL2);
-    mmu_regs.TCR[EL3] = cpu.read_register(Qemu::API::TCR, EL3);
 
     //? Section G8.2.167 - TTBR0, Translation Table Base Register 0
     //? Section G8.2.168 - TTBR1, Translation Table Base Register 1
     mmu_regs.TTBR0[EL1] = cpu.read_register(Qemu::API::TTBR0, EL1);
     mmu_regs.TTBR1[EL1] = cpu.read_register(Qemu::API::TTBR1, EL1);
-    mmu_regs.TTBR0[EL2] = cpu.read_register(Qemu::API::TTBR0, EL2);
-    mmu_regs.TTBR1[EL2] = cpu.read_register(Qemu::API::TTBR1, EL2);
-    mmu_regs.TTBR0[EL3] = cpu.read_register(Qemu::API::TTBR0, EL3);
 
     //? Section D23.2.74 - AArch64 Memory Model Feature Register 0
     mmu_regs.ID_AA64MMFR0_EL1 = cpu.read_register(Qemu::API::ID_AA64MMFR0, EL1);
 
-    DBG_(VVerb, (<< "Initializing mmu registers from QEMU...." << mmu_regs.TCR[EL1]));
+    fm_print_mmu_regs(&mmu_regs);
+
     return (mmu_regs.TCR[EL1] != 0);
 }
 
-bool
-mmu_t::IsExcLevelEnabled(uint8_t EL) const
-{
-    DBG_Assert(EL > 0 && EL <= 3, (<< "ERROR, ARM MMU: Transl. Request Not Supported at Invalid EL = " << EL));
-    return extractSingleBitAsBool(mmu_regs.SCTLR[EL], aarch64_bit_configs.M_Bit);
-}
 void
 mmu_t::setupAddressSpaceSizesAndGranules(void)
 {

diff --git a/components/MMU/pageWalk.cpp b/components/MMU/pageWalk.cpp
@@ -256,6 +256,14 @@ PageWalk::InitialTranslationSetup(TranslationTransport& aTranslation)
 
     uint8_t EL = statefulPointer->ELRegime;
 
+
+     /**
+      * Bryan Perdrizat
+      *      EL2 and EL3 are not setted up because QFlex is not (yet)
+      *      supporting well EL2 (hypervisor) mode well.
+      */
+    DBG_Assert(EL <= 1);
+
     // Handle a case where for Linux, the page table of EL0 is in EL1's register.
     if (EL == 0) {
         DBG_Assert(statefulPointer->isBR0);

diff --git a/components/uArch/CoreModel/construct.cpp b/components/uArch/CoreModel/construct.cpp
@@ -441,24 +441,28 @@ void
 CoreImpl::setSP_el(uint8_t anId, uint64_t aVal)
 {
     DBG_Assert(0 <= anId && anId < 4, (<< "Out of bound access with index = " << anId));
+    DBG_Assert(anId < 2, (<< "Unhandled simulation of hypervisor mode"));
     theSP_el[anId] = aVal;
 }
 uint64_t
 CoreImpl::getSP_el(uint8_t anId)
 {
     DBG_Assert(0 <= anId && anId < 4, (<< "Out of bound access with index = " << anId));
+    DBG_Assert(anId < 2, (<< "Unhandled simulation of hypervisor mode"));
     return theSP_el[anId];
 }
 void
 CoreImpl::setSPSR_el(uint8_t anId, uint64_t aVal)
 {
     DBG_Assert(0 <= anId && anId < 4, (<< "Out of bound access with index = " << anId));
+    DBG_Assert(anId < 2, (<< "Unhandled simulation of hypervisor mode"));
     theSPSR_EL[anId] = aVal;
 }
 uint64_t
 CoreImpl::getSPSR_el(uint8_t anId)
 {
     DBG_Assert(0 <= anId && anId < 4, (<< "Out of bound access with index = " << anId));
+    DBG_Assert(anId < 2, (<< "Unhandled simulation of hypervisor mode"));
     return theSPSR_EL[anId];
 }
 uint32_t
@@ -514,6 +518,7 @@ CoreImpl::setSCTLR_EL(uint8_t anId, uint64_t aSCTLR_EL)
 uint64_t
 CoreImpl::getSCTLR_EL(uint8_t anId)
 {
+    DBG_Assert(anId < 2, (<< "Unhandled simulation of hypervisor mode"));
     return theSCTLR_EL[anId];
 }
 void
@@ -524,7 +529,8 @@ CoreImpl::setHCREL2(uint64_t aHCREL2)
 uint64_t
 CoreImpl::getHCREL2()
 {
-    return theHCR_EL2;
+    DBG_Assert(false, (<< "Unhandled simulation of hypervisor mode"));
+    return 0;
 }
 void
 CoreImpl::setException(Flexus::Qemu::API::exception_t anEXP)