fix: Read TTBR0_EL1 when EL is 0

parsa-epfl · Sep 26, 2024 · ebccb72 · ebccb72
1 parent c43a822
commit ebccb72
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Showing 2 changed files with 9 additions and 0 deletions.
diff --git a/components/MMU/TTResolvers.cpp b/components/MMU/TTResolvers.cpp
@@ -17,6 +17,7 @@ TTResolver::TTResolver(bool abro, _TTResolver_Shptr_T aGranule, address_t aTTBR,
   , PAddressWidth(PAddrWidth)
   , regimeTG(aGranule)
 {
+    DBG_Assert(aTTBR != 0);
     TnSz          = regimeTG->getIAddrOffset();
     IAddressWidth = 64 - regimeTG->getIAddrSize();
 }
@@ -26,6 +27,7 @@ address_t
 TTResolver::resolve(address_t inputAddress)
 {
     DBG_(VVerb, (<< "TTBR RAW: " << std::hex << RawTTBRReg << std::dec));
+    DBG_Assert(RawTTBRReg != 0);
     address_t output = extractBitsWithBounds(RawTTBRReg, TTBR_MSB, TTBR_LSB);
     DBG_(VVerb, (<< "TTBR EXTRACT: " << std::hex << output << std::dec));
     output = output << TTBR_LSB;

diff --git a/components/MMU/pageWalk.cpp b/components/MMU/pageWalk.cpp
@@ -255,6 +255,13 @@ PageWalk::InitialTranslationSetup(TranslationTransport& aTranslation)
     statefulPointer->ELRegime             = currentEL();
 
     uint8_t EL = statefulPointer->ELRegime;
+
+    if (EL == 0) {
+        DBG_Assert(statefulPointer->isBR0);
+        // For Linux, the page table of El0 is in EL1's register.
+        EL = 1;
+    };
+
     uint64_t initialTTBR;
     if (statefulPointer->isBR0)
         initialTTBR = theMMU->mmu_regs.TTBR0[EL];