fix: L1i miss checkpoint load (#67)

* fix: uFetch's instruction cache should load the checkpoint * chores: add comments to assertion check --------- Co-authored-by: Bryan Perdrizat <[email protected]>
parsa-epfl · Sep 30, 2024 · f5f417a · f5f417a
1 parent 125af83
commit f5f417a
Show file tree

Hide file tree

Showing 2 changed files with 25 additions and 4 deletions.
diff --git a/components/uFetch/SimCache.hpp b/components/uFetch/SimCache.hpp
@@ -2,6 +2,7 @@
 #define FLEXUS_UFETCH_SIMCACHE
 #include "components/CommonQEMU/seq_map.hpp"
 #include "core/checkpoint/json.hpp"
+#include "core/debug/debug.hpp"
 
 #include <fstream>
 using json = nlohmann::json;
@@ -51,13 +52,21 @@ struct SimCache
         ifs >> checkpoint;
         uint32_t tag_shift = LOG2(theCache.sets());
 
+        DBG_Assert((uint64_t)theCacheAssoc == checkpoint["associativity"]);
+        DBG_Assert((uint64_t)theCache.sets() == checkpoint["tags"].size());
+
         for (std::size_t i{ 0 }; i < theCache.sets(); i++) {
-            for (uint32_t j = 0; j < checkpoint["tags"].at(i).size(); j++) {
+            for (uint32_t j = checkpoint["tags"].at(i).size()-1; j != 0; j--) {
+                // The reason why we reverse the order is because we want to insert the least recent tags first
                 bool dirty    = checkpoint["tags"].at(i).at(j)["dirty"];
+                DBG_Assert(!dirty, (<< "Only non dirty block should have been saved, therefore imported"));
                 bool writable = checkpoint["tags"].at(i).at(j)["writable"];
+                DBG_Assert(!writable, (<< "Only non writeable block should have been saved, therefore imported"));
                 uint64_t tag  = checkpoint["tags"].at(i).at(j)["tag"];
 
                 theCache.insert(std::make_pair((tag << tag_shift) | i, 0));
+
+                DBG_(Dev, (<< "Loading tag " << std::hex << ((tag << tag_shift) | i)));
             }
         }
 

diff --git a/components/uFetch/uFetch.cpp b/components/uFetch/uFetch.cpp
@@ -555,7 +555,7 @@ class FLEXUS_COMPONENT(uFetch)
             }
         }
     }
-    void initialize()
+    void initialize() override
     {
 
         theI.init(cfg.Size, cfg.Associativity, cfg.ICacheLineSize, statName());
@@ -572,8 +572,8 @@ class FLEXUS_COMPONENT(uFetch)
         theIcachePrefetch.resize(cfg.Threads);
         theLastPrefetchVTagSet.resize(cfg.Threads);
     }
-    void finalize() {}
-    void drive(interface::uFetchDrive const&)
+    void finalize() override {}
+    void drive(interface::uFetchDrive const&) override
     {
 
         bool garbage = true;
@@ -781,6 +781,18 @@ class FLEXUS_COMPONENT(uFetch)
             default: DBG_Assert(false, Comp(*this)(<< "FETCH UNIT: Unhandled message received: " << *reply));
         }
     }
+
+    void loadState(std::string const& aDirName) override
+    {
+        // I need to load the instruction cache here.
+        this->theI.loadState(aDirName + "/" + statName() + "-L1i.json");
+    }
+
+    void saveState(std::string const& aDirName) override
+    {
+        // Not implemented.
+
+    }
 };
 
 } // END OF NAMESPACE nuFETCH