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scr1
scr1 PublicForked from syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
SystemVerilog 1
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core-v-verif
core-v-verif PublicForked from openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Assembly
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cv32e40p
cv32e40p PublicForked from openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SystemVerilog
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core-v-docs
core-v-docs PublicForked from openhwgroup/programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
HTML 1
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cvfpu
cvfpu PublicForked from openhwgroup/cvfpu
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
SystemVerilog
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core-v-sw
core-v-sw PublicForked from openhwgroup/core-v-sw
Main Repo for the OpenHW Group Software Task Group
96 contributions in the last year
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