Pinned Loading

1. fpga-pc-uart fpga-pc-uart Public

   Demonstrates reliable data transfer between an FPGA and a computer (PC) via UART handshake protocol

   Verilog 1

2. rtl-design rtl-design Public

   RTL projects for various applications

   SystemVerilog 1

3. rtl-verif rtl-verif Public

   Projects focussing on RTL verification (UVM, SV, UVM Framework etc.,)

   SystemVerilog

4. ml-projects ml-projects Public

   Exploring Machine Learning Concepts through Projects

   Jupyter Notebook

5. RISC-V-CPU RISC-V-CPU Public

   RISC-V CPU Design Using TL-Verilog

   Verilog 2