Add XRT and ACCL support for Xilinx FPGAs

Major additions in this release are:

• add support for host codes using the XRT C++ API and HLS C/C++ device code for Xilinx FPGAs.
• add support for ACCL in b_eff, LINPACK, and PTRANS based on the XRT.

Full Changelog: v0.5.1...v0.6

Full compatibility to cl2.hpp

This release contains minor changes in the host code compared to v0.5.
All benchmarks can now use cl2.hpp. For compatibility, cl.hpp can still be used with the configuration flag -DUSE_DEPRECATED_HPP_HEADER=Yes.

PCIe+MPI communication

Implement multi-FPGA benchmarks that use PCIe+MPI for communication to achieve compatibility for Intel and Xilinx FPGAs.

Add Multi-FPGA Support

This release adds support for the execution and validation of all benchmarks on multiple FPGAs.
It also contains implementations of the b_eff, PTRANS and HPL benchmark for Intel FPGAs.

Improvement of GEMM and FFT

Next to minor changes, bug fixes, and improvements, this release introduces the following major changes:

• Optimize FFT for Xilinx up to a size of LOG_FFT_SIZE=9
• Kernel replication support for GEMM and FFT
• Remove git submodules and instead fetch dependencies using CMake. This eliminates the need to check out out the git repository to build the benchmarks.

Updated Evaluation Version

This version contains a refactored host code and build process and also brings support for SVM.

Initial Version

This Release contains the code that was used in the publication arXiv:2004.11059.