See Vitis™ Development Environment on xilinx.com |
Version: Vitis 2023.1
The tutorials under the AI Engine Development help you learn how to target, develop, and deploy advanced algorithms using a Versal AI Engine array in conjunction with PL IP/kernels and software applications running on the embedded processors. In order to successfully deploy AI Engine applications in hardware, you need to be aware of the Vitis and AI Engine tools and flows.
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The AI Engine Development Feature Tutorials highlight specific features and flows that help develop AI Engine applications.
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The AI Engine Development Design Tutorials showcase the two major phases of AI Engine application development: architecting the application and developing the kernels. Both these phases are demonstrated in these tutorials.
These tutorials target the VCK190 board. The table below lists the tutorials available, and the features and flows showcased in all of these tutorials. The various columns correspond to specific features/flows supported in these tutorials and will help you identify tutorials that showcase specific flows and features that you are interested in.
IMPORTANT: Before beginning the tutorial make sure you have read and followed the Vitis Software Platform Release Notes (v2023.1) for setting up software and installing the VCK190 base platform.
Run the following steps to setup environment ( NOT apply to tutorials that do not use the VCK190 base platform ):
- Set up your platform by running the
xilinx-versal-common-v2023.1/environment-setup-cortexa72-cortexa53-xilinx-linuxscript as provided in the platform download. This script sets up theSYSROOTandCXXvariables. If the script is not present, you must run thexilinx-versal-common-v2023.1/sdk.sh. - Set up your
ROOTFSto point to thexilinx-versal-common-v2023.1/rootfs.ext4. - Set up your
IMAGEto point toxilinx-versal-common-v2023.1/Image. - Set up your
PLATFORM_REPO_PATHSenvironment variable based upon where you downloaded the platform.
| Tutorial | Platform | OS | IDE Flow | Libraries Used | HLS Kernel | x86 simulator | aie simulator | SW Emu | HW Emu | HW | Event Trace in HW | Profile in HW |
| AI Engine A-to-Z Flow for Linux | Base / Custom | Linux | MM2S / S2MM | Yes | Yes | Yes | Yes | Yes | ||||
| A to Z Bare-metal Flow | Custom | Baremetal | Vivado & Vitis IDE |
MM2S / S2MM | Yes | Yes | Yes | |||||
| Using GMIO with AIE | Base | Linux | Yes | Yes | Yes | Yes | ||||||
| Runtime Parameter Reconfiguration | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | ||||||
| Packet Switching | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | ||||||
| AIE Versal Integration | Base | Linux | CLI / Vitis Unified IDE | MM2S / S2MM | Yes | Yes | Yes | Yes | Yes | |||
| Versal System Design Clocking | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | ||||||
| Using Floating-Point in the AIE | Base | Linux | Yes | |||||||||
| DSP Library Tutorial | Base | Linux | DSPLib | MM2S / S2MM Variant | Yes | |||||||
| Debug Walkthrough Tutorial | Base | Linux | Vitis IDE | Yes | Yes | Yes | Yes | Yes | Yes | Yes | ||
| AIE DSPLib and Model Composer | Base | Linux | Simulink | DSPLib | MM2S / S2MM | Yes | Yes | |||||
| Versal Emulation Waveform Analysis | Base | Linux | Traffic Generators | Yes | ||||||||
| AXIS External Traffic Generator | Base | Linux | DSPLib | MM2S / S2MM | Yes | Yes | ||||||
| AIE Performance and Deadlock Analysis | Base | Linux | Yes | Yes | Yes | Yes | ||||||
| Implementing an IIR Filter on the AIE | Base | Linux | Vitis IDE | Yes | Yes | |||||||
| Post-Link Recompile of an AIE Application | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | ||||||
| Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows | Base | Linux | MM2S / S2MM / PolarClip | Yes | Yes | Yes | Yes | |||||
| Using RTL IP with AI Engines | Custom | Linux | MM2S / S2MM | Yes | Yes | |||||||
| Using Verilog Traffic Generators in AIE Simulation | Base | Linux | Vivado | Yes | Yes |
| Tutorial | Platform | OS | IDE Flow | Libraries Used | HLS Kernel | x86 simulator | aie simulator | SW Emu | HW Emu | HW | Event Trace in HW | Profile in HW |
| Versal Custom Thin Platform Extensible System | Custom | Linux | MM2S / S2MM / VADD | Yes | Yes | |||||||
| LeNet Tutorial | Base | Linux | MM2S / S2MM | Yes | Yes | Yes | Yes | |||||
| Super Sampling Rate FIR Filters | Base | Linux | Yes | |||||||||
| Beamforming Design | Base | Linux | Yes | Yes | Yes | Yes | ||||||
| Polyphase Channelizer | Base | Linux | MM2S / S2MM | Yes | Yes | |||||||
| 2D-FFT | Base | Linux | DSPLib | PL Data Generator and Checker | Yes | Yes | Yes | Yes | ||||
| FIR Filter | Base | Linux | DSPLib | PL Data Generator and Checker | Yes | Yes | Yes | Yes | ||||
| N-Body Simulator | Base | Linux | PL Datamover | Yes | Yes | Yes | ||||||
| Versal GeMM Implementation | Base | Linux | DSPLib | Datamover | Yes | Yes | Yes | Yes |
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