Verilator width error with mux select expression

[leonardt]

Magma

import magma as m


class Foo(m.Circuit):
    io = m.IO(I=m.In(m.UInt[8]), O=m.Out(m.UInt[8]))
    io.O @= m.mux(
        [io.I + 1, io.I - 1],
        ~io.I.reduce_and() & io.I[0]
    )


m.compile('build/Foo', Foo, output="mlir-verilog")

MLIR

module attributes {circt.loweringOptions = "locationInfoStyle=none"} {
    hw.module @Foo(%I: i8) -> (O: i8) {
        %0 = hw.constant 1 : i8
        %1 = comb.add %I, %0 : i8
        %2 = hw.constant 1 : i8
        %3 = comb.sub %I, %2 : i8
        %5 = hw.constant -1 : i8
        %4 = comb.icmp eq %I, %5 : i8
        %7 = hw.constant -1 : i1
        %6 = comb.xor %7, %4 : i1
        %8 = comb.extract %I from 0 : (i8) -> i1
        %9 = comb.and %6, %8 : i1
        %11 = hw.array_create %3, %1 : i8
        %10 = hw.array_get %11[%9] : !hw.array<2xi8>, i1
        hw.output %10 : i8
    }
}

verilog

module Foo(
  input  [7:0] I,
  output [7:0] O);

  wire [1:0][7:0] _GEN = {{I - 8'h1}, {I + 8'h1}};
  assign O = _GEN[I != 8'hFF & I[0]];
endmodule

lint result

❯ verilator --lint-only Foo.v
%Warning-WIDTH: Foo.v:7:30: Operator AND expects 32 or 4 bits on the LHS, but LHS's NEQ generates 1 bits.
                          : ... In instance Foo
    7 |   assign O = _GEN[I != 8'hFF & I[0]];
      |                              ^
                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: Foo.v:7:30: Operator AND expects 32 or 4 bits on the RHS, but RHS's SEL generates 1 bits.
                          : ... In instance Foo
    7 |   assign O = _GEN[I != 8'hFF & I[0]];
      |                              ^
%Error: Exiting due to 2 warning(s)

[leonardt]

@rsetaluri given your knowledge of the verilog width inference rules, is this an issue with the way the verilog is generated? Or is it an issue with the verilator implementation of the width inference?

[leonardt]

This is potentially related: verilator/verilator#3374