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175 Open 314 Closed
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Issues list

Warning when wiring enable using __call__ syntax
#1364 opened Mar 11, 2024 by leonardt
1
Migrate output_filelist attribute to use emit dialect
#1359 opened Mar 11, 2024 by leonardt
1
Installation on latest main branch is failing
#1358 opened Mar 4, 2024 by rkshthrmsh
5
[IO] Unintuitive behavior with IO objects
#1349 opened Jan 24, 2024 by leonardt
@rsetaluri
1
Automatic formatter
#1341 opened Nov 21, 2023 by leonardt
@leonardt @rsetaluri
1
Should sv=True be default for mlir-verilog?
#1339 opened Nov 17, 2023 by leonardt
1
Cannot pickle (or jsonify) magma structures
#1334 opened Oct 25, 2023 by steveri
1
Reducing compile time
#1328 opened Sep 25, 2023 by rkshthrmsh
1
Add support for key/value pair arguments to product constructor
#1319 opened Sep 22, 2023 by leonardt
@leonardt
[RFC] Mantle and FPGAs
#1300 opened Aug 8, 2023 by leonardt
13
[Circuit] Detect overwriting of self.io in the presence of local references
#1298 opened Aug 7, 2023 by rsetaluri
@rsetaluri
7
[CI] Speed up testing
#1295 opened Jul 27, 2023 by rsetaluri
1
[CompileGuard] Compile guard select issues
#1291 opened Jul 26, 2023 by rsetaluri
2 tasks
@rsetaluri
[Circuit] Add get_instance() method on circuits to get instances by name
#1262 opened Apr 13, 2023 by rsetaluri
@rsetaluri
Consolidate and update examples
#1259 opened Apr 4, 2023 by rsetaluri
5 tasks
@leonardt @rsetaluri
[When] Return inside of when statement produces counter-intuitive results
#1258 opened Apr 3, 2023 by rsetaluri
@leonardt
1
[MLIR][Bind2] Filelist only written out when split_verilog enabled
#1256 opened Mar 24, 2023 by rsetaluri
@rsetaluri
[MLIR] when support for flatten_all_tuples
#1253 opened Mar 22, 2023 by leonardt
1
1
Verilator width error with mux select expression
#1247 opened Mar 15, 2023 by leonardt
2
Avoid bit-blasting in conversions
#1245 opened Mar 13, 2023 by leonardt
Type annotations for magma functions
#1217 opened Dec 23, 2022 by rkshthrmsh
1
Registering product types
#1215 opened Dec 22, 2022 by rkshthrmsh
4
[Debug] uinspect dynamic frame walk
#1210 opened Dec 15, 2022 by leonardt
@leonardt
Circuit sublasses with arguments or verilog modules with parameters
#1195 opened Nov 19, 2022 by rkshthrmsh
2
[MLIR] How to add attribute and source location
#1182 opened Nov 9, 2022 by Kuree
22
ProTip! Exclude everything labeled bug with -label:bug.