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math: Fix sqrt calc on IA32 #282

Merged
merged 1 commit into from
Aug 24, 2023
Merged

math: Fix sqrt calc on IA32 #282

merged 1 commit into from
Aug 24, 2023

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gerard5
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@gerard5 gerard5 commented Aug 19, 2023

This change assumes that the fsqrt calculation is performed for double precision FP and rounded to the nearest (even) value. To achieve this, the FPU control word is set accordingly at the sqrt computation time. All exceptions are enabled: any underflow, overflow, /0, invalid precission, etc during sqrt calculation will throw an exception.
All other settings (exceptions mask, infinity control) in FPU control word are inherited (not changed).

Fixes phoenix-rtos/phoenix-rtos-project#800

JIRA: RTOS-562

Description

Motivation and Context

Types of changes

  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

How Has This Been Tested?

  • Already covered by automatic testing.
  • New test added: (add PR link here).
  • Tested by hand on: ia32-generic.

Checklist:

  • My change requires a change to the documentation.
  • I have updated the documentation accordingly.
  • I have added tests to cover my changes.
  • All new and existing linter checks and tests passed.
  • My changes generate no new compilation warnings for any of the targets.

Special treatment

  • This PR needs additional PRs to work (list the PRs, preferably in merge-order).
  • I will merge this PR by myself when appropriate.

@gerard5 gerard5 self-assigned this Aug 19, 2023
@gerard5 gerard5 marked this pull request as ready for review August 19, 2023 20:52
adamdebek
adamdebek previously approved these changes Aug 21, 2023
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LGTM, passed my sqrt tests, which soon will be in review

@kemonats
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Small comment.
From the documentation:

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 1: Basic Architecture

8.1.5.1 x87 FPU Floating-Point Exception Mask Bits

The exception-flag mask bits (bits 0 through 5 of the x87 FPU control word) mask the 6 floating-point exception
flags in the x87 FPU status word. When one of these mask bits is set, its corresponding x87 FPU floating-point
exception is blocked from being generated.

@gerard5
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gerard5 commented Aug 21, 2023

Small comment. From the documentation:
..

You're right, in the meantime I modified this a bit: to inherit the control word settings except the ones I want to set (RC, PC). This change was posted to test if it fixes the issue. I will push a patch-set regarding the changes I write about, I will be grateful if you take a look.

This change assumes that the `fsqrt` calculation is performed
for double precision FP and rounded to the nearest (even) value.
To achieve this, the FPU control word is set accordingly at
the sqrt computation time. All other settings in FPU control word
are inherited (not changed).

JIRA: RTOS-562
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@agkaminski agkaminski left a comment

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LGTM

@gerard5 gerard5 merged commit 90d2bf0 into master Aug 24, 2023
25 checks passed
@gerard5 gerard5 deleted the gerard5/RTOS-562 branch August 24, 2023 06:47
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ia32 hardware sqrt return totally wrong values
4 participants