add armv8m architecture port + nrf9160 target

hal/armv8m/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile for Phoenix-RTOS kernel (ARMv8M HAL)
+#
+# Copyright 2022 Phoenix Systems
+#
+
+
+ifneq (, $(findstring nrf, $(TARGET_SUBFAMILY)))
+    include hal/armv8m/nrf/Makefile
+    CFLAGS += -Ihal/armv8m
+endif
+
+OBJS += $(addprefix $(PREFIX_O)hal/armv8m/, string.o spinlock.o cpu.o hal.o pmap.o exceptions.o)

hal/armv8m/arch/cpu.h

@@ -0,0 +1,241 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system kernel
+ *
+ * CPU related routines
+ *
+ * Copyright 2014, 2017, 2022 Phoenix Systems
+ * Author: Jacek Popko, Pawel Pisarczyk, Aleksander Kaminski, Damian Loewnau
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+#ifndef _HAL_ARMV8M_CPU_H_
+#define _HAL_ARMV8M_CPU_H_
+
+
+#if defined(__CPU_NRF9160)
+#define CPU_NRF91
+#endif
+
+#include "types.h"
+
+#define SIZE_PAGE 0x200
+
+#ifndef SIZE_USTACK
+#define SIZE_USTACK (3 * SIZE_PAGE)
+#endif
+
+#ifndef SIZE_KSTACK
+#define SIZE_KSTACK (4 * SIZE_PAGE)
+#endif
+
+/* values based on EXC_RETURN requirements */
+#define RET_HANDLER_MSP 0xfffffff1u
+#define RET_THREAD_MSP  0xfffffff9u
+#define RET_THREAD_PSP  0xfffffffdu
+#define HWCTXSIZE       8
+#define USERCONTROL     0x3u
+
+#ifndef __ASSEMBLY__
+
+
+#define SYSTICK_INTERVAL 1000
+
+
+#define PUTONSTACK(kstack, t, v) \
+	do { \
+		(kstack) -= (sizeof(t) + 3) & ~0x3u; \
+		*((t *)kstack) = (v); \
+	} while (0)
+
+
+#define GETFROMSTACK(ustack, t, v, n) \
+	do { \
+		ustack = (void *)(((ptr_t)ustack + sizeof(t) - 1) & ~(sizeof(t) - 1)); \
+		(v) = *(t *)ustack; \
+		ustack += (sizeof(t) + 3) & ~0x3u; \
+	} while (0)
+
+
+typedef struct {
+	u32 r0;
+	u32 r1;
+	u32 r2;
+	u32 r3;
+	u32 r12;
+	u32 lr;
+	u32 pc;
+	u32 psr;
+} cpu_hwContext_t;
+
+
+typedef struct _cpu_context_t {
+	u32 savesp_s;
+	u32 padding;
+
+	/* Saved by ISR */
+	u32 psp;
+	u32 r4;
+	u32 r5;
+	u32 r6;
+	u32 r7;
+	u32 r8;
+	u32 r9;
+	u32 r10;
+	u32 r11;
+	u32 irq_ret;
+
+	/* Saved by hardware */
+	cpu_hwContext_t hwctx;
+
+} cpu_context_t;
+
+
+static inline void hal_cpuDisableInterrupts(void)
+{
+	__asm__ volatile("cpsid if");
+}
+
+
+static inline void hal_cpuEnableInterrupts(void)
+{
+	__asm__ volatile("cpsie if");
+}
+
+
+static inline void hal_cpuHalt(void)
+{
+	__asm__ volatile("\
+		wfi; \
+		nop; ");
+}
+
+
+/* bit operations */
+
+
+static inline unsigned int hal_cpuGetLastBit(unsigned long v)
+{
+	int pos;
+	/* clang-format off */
+	__asm__ volatile("clz %0, %1" : "=r" (pos) : "r" (v));
+
+	return 31 - pos;
+}
+
+
+static inline unsigned int hal_cpuGetFirstBit(unsigned long v)
+{
+	unsigned pos;
+
+	__asm__ volatile("\
+		rbit %0, %1; \
+		clz  %0, %0;" : "=r" (pos) : "r" (v));
+
+	return pos;
+}
+
+
+/* context management */
+
+static inline void hal_cpuSetCtxGot(cpu_context_t *ctx, void *got)
+{
+	ctx->r9 = (u32)got;
+}
+
+
+static inline void hal_cpuSetGot(void *got)
+{
+	__asm__ volatile("mov r9, %0" :: "r" (got));
+}
+
+
+static inline void *hal_cpuGetGot(void)
+{
+	void *got;
+
+	__asm__ volatile("mov %0, r9" : "=r" (got));
+
+	return got;
+}
+
+
+static inline void hal_cpuRestore(cpu_context_t *curr, cpu_context_t *next)
+{
+	curr->savesp_s = (u32)next;
+}
+
+
+static inline void hal_cpuSetReturnValue(cpu_context_t *ctx, int retval)
+{
+	ctx->hwctx.r0 = retval;
+}
+
+
+static inline u32 hal_cpuGetPC(void)
+{
+	void *pc;
+
+	__asm__ volatile("mov %0, pc" : "=r" (pc));
+	/* clang-format on */
+
+	return (u32)pc;
+}
+
+
+static inline void _hal_cpuSetKernelStack(void *kstack)
+{
+}
+
+
+static inline void *hal_cpuGetSP(cpu_context_t *ctx)
+{
+	return (void *)ctx;
+}
+
+
+static inline void *hal_cpuGetUserSP(cpu_context_t *ctx)
+{
+	return (void *)ctx->psp;
+}
+
+
+static inline int hal_cpuSupervisorMode(cpu_context_t *ctx)
+{
+	return ((ctx->irq_ret & (1 << 2)) == 0) ? 1 : 0;
+}
+
+
+static inline int hal_cpuPushSignal(void *kstack, void (*handler)(void), int sig)
+{
+	return 0;
+}
+
+
+/* core management */
+
+
+static inline unsigned int hal_cpuGetID(void)
+{
+	return 0;
+}
+
+
+static inline unsigned int hal_cpuGetCount(void)
+{
+	return 1;
+}
+
+
+static inline void cpu_sendIPI(unsigned int cpu, unsigned int intr)
+{
+}
+
+
+#endif
+
+#endif

hal/armv8m/arch/exceptions.h

@@ -0,0 +1,46 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system kernel
+ *
+ * Exceptions handling
+ *
+ * Copyright 2022 Phoenix Systems
+ * Author: Damian Loewnau
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+#ifndef _HAL_ARMV8M_EXCEPTIONS_H_
+#define _HAL_ARMV8M_EXCEPTIONS_H_
+
+#include "types.h"
+#include "cpu.h"
+
+#define EXC_DEFAULT 128
+
+#define EXC_UNDEFINED 3
+
+#define SIZE_CTXDUMP 512 /* Size of dumped context */
+
+
+typedef struct _exc_context_t {
+	/* Saved by ISR */
+	u32 psp;
+	u32 r4;
+	u32 r5;
+	u32 r6;
+	u32 r7;
+	u32 r8;
+	u32 r9;
+	u32 r10;
+	u32 r11;
+	u32 excret;
+
+	/* Saved by hardware */
+	cpu_hwContext_t mspctx;
+} exc_context_t;
+
+#endif

hal/armv8m/arch/interrupts.h

@@ -0,0 +1,38 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system kernel
+ *
+ * Interrupt handling
+ *
+ * Copyright 2016, 2017, 2020, 2022 Phoenix Systems
+ * Author: Pawel Pisarczyk, Artur Wodejko, Hubert Buczynski, Damian Loewnau
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+
+#ifndef _HAL_ARMV8M_INTERRUPTS_H_
+#define _HAL_ARMV8M_INTERRUPTS_H_
+
+#include "cpu.h"
+
+#define SVC_IRQ     11
+#define PENDSV_IRQ  14
+#define SYSTICK_IRQ 15
+
+
+typedef struct _intr_handler_t {
+	struct _intr_handler_t *next;
+	struct _intr_handler_t *prev;
+	/* irq */
+	unsigned int n;
+	/* handler function */
+	int (*f)(unsigned int, cpu_context_t *, void *);
+	void *data;
+	void *got;
+} intr_handler_t;
+
+#endif