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gr716: remove unnecessary gpio configuration
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JIRA: RTOS-535
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lukileczo committed Jul 25, 2023
1 parent a707c0b commit 486d752
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Showing 4 changed files with 24 additions and 78 deletions.
48 changes: 9 additions & 39 deletions devices/uart-gr716/uart.c
Original file line number Diff line number Diff line change
Expand Up @@ -115,43 +115,6 @@ static int uart_irqHandler(unsigned int n, void *data)
}


static int uart_setPin(u8 pin)
{
io_cfg_t uartCfg;
uartCfg.opt = 0x1;
uartCfg.pin = pin;
uartCfg.pullup = 0;
uartCfg.pulldn = 0;

switch (pin) {
case UART0_TX:
case UART1_TX:
/* pins used for SRAM */
return -1;
case UART2_TX:
case UART3_TX:
case UART4_TX:
case UART5_TX:
uartCfg.dir = GPIO_DIR_OUT;
break;
case UART0_RX:
case UART1_RX:
/* pins used for SRAM */
return -1;
case UART2_RX:
case UART3_RX:
case UART4_RX:
case UART5_RX:
uartCfg.dir = GPIO_DIR_IN;
break;
default:
return -1;
}

return _gr716_ioCfg(&uartCfg);
}


/* From datasheet:
* appropriate formula to calculate the scaler for desired baudrate,
* using integer division where the remainder is discarded:
Expand Down Expand Up @@ -294,6 +257,7 @@ static int uart_map(unsigned int minor, addr_t addr, size_t sz, int mode, addr_t
static int uart_init(unsigned int minor)
{
uart_t *uart;
iomux_cfg_t cfg;
/* When running external SRAM, UART0 and UART1 pins cannot be used */
if (minor == 0 || minor == 1) {
return EOK;
Expand All @@ -312,8 +276,14 @@ static int uart_init(unsigned int minor)

_gr716_cguClkEnable(cgu_primary, cgudev_apbuart0 + minor);

uart_setPin(info[minor].txPin);
uart_setPin(info[minor].rxPin);
cfg.opt = 0x1;
cfg.pullup = 0;
cfg.pulldn = 0;
cfg.pin = info[minor].txPin;
_gr716_iomuxCfg(&cfg);

cfg.pin = info[minor].rxPin;
_gr716_iomuxCfg(&cfg);

lib_cbufInit(&uart->cbuffRx, uart->dataRx, BUFFER_SIZE);

Expand Down
38 changes: 11 additions & 27 deletions hal/sparcv8leon3/gr716/console.c
Original file line number Diff line number Diff line change
Expand Up @@ -53,31 +53,6 @@ void hal_consolePrint(const char *s)
}


static int console_setPin(u8 pin)
{
int err = 0;
io_cfg_t uartCfg;
uartCfg.opt = 0x1;
uartCfg.pin = pin;
uartCfg.pullup = 0;
uartCfg.pulldn = 0;

switch (pin) {
case UART_CONSOLE_TX:
uartCfg.dir = GPIO_DIR_OUT;
break;
case UART_CONSOLE_RX:
uartCfg.dir = GPIO_DIR_IN;
break;
default:
err = -1;
break;
}

return err == 0 ? _gr716_ioCfg(&uartCfg) : err;
}


static u32 console_calcScaler(u32 baud)
{
u32 scaler = (SYSCLK_FREQ / (baud * 8 + 7));
Expand All @@ -87,8 +62,17 @@ static u32 console_calcScaler(u32 baud)

void console_init(void)
{
console_setPin(UART_CONSOLE_TX);
console_setPin(UART_CONSOLE_RX);
iomux_cfg_t cfg;

cfg.opt = 0x1;
cfg.pullup = 0;
cfg.pulldn = 0;
cfg.pin = UART_CONSOLE_TX;
_gr716_iomuxCfg(&cfg);

cfg.pin = UART_CONSOLE_RX;
_gr716_iomuxCfg(&cfg);

_gr716_cguClkEnable(cgu_primary, UART_CONSOLE_CGU);
halconsole_common.uart = UART_CONSOLE_BASE;
*(halconsole_common.uart + uart_ctrl) = TX_EN;
Expand Down
11 changes: 2 additions & 9 deletions hal/sparcv8leon3/gr716/gr716.c
Original file line number Diff line number Diff line change
Expand Up @@ -138,18 +138,11 @@ static void _gr716_pllSetDefault(void)
}


/* Enable (1) / disable (0) interrupts from PLL and clock logic */
void _gr716_pllIntCfg(u8 en)
{
*(gr716_common.pll_base + pll_ctrl) = en;
}


int _gr716_ioCfg(io_cfg_t *ioCfg)
int _gr716_iomuxCfg(iomux_cfg_t *ioCfg)
{
vu32 oldCfg;

if (ioCfg->pin > 63 || gpio_setPinDir(ioCfg->pin, ioCfg->dir) < 0) {
if (ioCfg->pin > 63) {
return -1;
}

Expand Down
5 changes: 2 additions & 3 deletions hal/sparcv8leon3/gr716/gr716.h
Original file line number Diff line number Diff line change
Expand Up @@ -41,16 +41,15 @@ cgudev_gradc3, cgudev_gradc4, cgudev_gradc5, cgudev_gradc6, cgudev_gradc7, cgude
typedef struct {
u8 pin;
u8 opt; /* GR716 manual section 2.5 */
u8 dir;
u8 pullup;
u8 pulldn;
} io_cfg_t;
} iomux_cfg_t;


extern void _gr716_softRst(void);


extern int _gr716_ioCfg(io_cfg_t *io_cfg);
extern int _gr716_iomuxCfg(iomux_cfg_t *ioCfg);


extern void _gr716_cguClkEnable(u32 cgu, u32 device);
Expand Down

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