riscv-sbi: implement basic SBI for RISC-V

Add basic implementation of SBI for RISC-V architecture,
suitable for use with Phoenix-RTOS on single core systems.

JIRA: RTOS-859

riscv-sbi/Makefile

@@ -0,0 +1,91 @@
+
+# Makefile for Phoenix SBI
+#
+# Copyright 2024 Phoenix Systems
+#
+# %LICENSE%
+#
+
+SIL ?= @
+MAKEFLAGS += --no-print-directory
+
+KERNEL=1
+
+include ../../phoenix-rtos-build/Makefile.common
+
+# check necessary variables
+ifeq ($(filter clean,$(MAKECMDGOALS)),)
+  ifeq ($(PAYLOAD_PATH),)
+    $(error PAYLOAD_PATH is not set)
+  endif
+  ifeq ($(PAYLOAD_ADDR),)
+    $(error PAYLOAD_ADDR is not set)
+  endif
+endif
+
+LDGEN ?= $(CC)
+
+CFLAGS += -I. -Iinclude
+CPPFLAGS += -DPAYLOAD_PATH=\"$(PAYLOAD_PATH)\"
+
+ifneq ($(FDT_PATH),)
+  CPPFLAGS += -DFDT_PATH=\"$(FDT_PATH)\"
+endif
+
+LDSFLAGS += -DPAYLOAD_ADDR=$(PAYLOAD_ADDR)
+
+OBJS :=
+
+include core/Makefile
+include devices/Makefile
+
+OBJS += $(addprefix $(PREFIX_O), entry.o)
+
+.PHONY: all clean
+
+.PRECIOUS: $(BUILD_DIR)%/.
+
+
+all: $(PREFIX_PROG_STRIPPED)sbi-$(TARGET_SUBFAMILY).elf $(PREFIX_PROG_STRIPPED)sbi-$(TARGET_SUBFAMILY).img
+
+
+$(PREFIX_PROG)sbi-$(TARGET_SUBFAMILY).elf: $(PREFIX_O)/sbi-$(TARGET_SUBFAMILY).ld $(OBJS) | $(PREFIX_PROG)/.
+	@echo "LD  $(@F)"
+	$(SIL)$(LD) $(CFLAGS) $(LDFLAGS) -Wl,-Map=$<.map -o $@ -Wl,-T,$^ -nostdlib -lgcc
+
+
+$(PREFIX_PROG_STRIPPED)%.hex: $(PREFIX_PROG_STRIPPED)%.elf
+	@echo "HEX $(@F)"
+	$(SIL)$(OBJCOPY) -O ihex $< $@
+
+
+$(PREFIX_PROG_STRIPPED)%.img: $(PREFIX_PROG_STRIPPED)%.elf
+	@echo "BIN $(@F)"
+	$(SIL)$(OBJCOPY) -O binary $< $@
+
+
+-include $(PREFIX_O)/sbi-$(TARGET_SUBFAMILY)*ld.d
+$(PREFIX_O)/sbi-$(TARGET_SUBFAMILY).ld: | $(PREFIX_O)/.
+	@echo "GEN $(@F)"
+	$(SIL)$(LDGEN) $(LDSFLAGS) -MP -MF $@.d -MMD -D__LINKER__ -undef -xc -E -P ld/$(TARGET_SUBFAMILY).ldt > $@
+	$(SIL)$(SED) -i.tmp -e 's`.*\.o[ \t]*:`$@:`' $@.d && rm $@.d.tmp
+
+
+$(PREFIX_O)/sbi-$(TARGET_SUBFAMILY)-%.ld: | $(PREFIX_O)/.
+	@echo "GEN $(@F)"
+	$(SIL)$(LDGEN) $(LDSFLAGS) -MP -MF $@.d -MMD -D__LINKER__ -D$* -undef -xc -E -P ld/$(TARGET_SUBFAMILY).ldt > $@
+	$(SIL)$(SED) -i.tmp -e 's`.*\.o[ \t]*:`$@:`' $@.d && rm $@.d.tmp
+
+
+%/.:
+	@echo "MKDIR $(@D)"
+	$(SIL)mkdir -p "$(@D)"
+
+
+clean:
+	@echo "rm -rf $(BUILD_DIR)"
+
+
+ifneq ($(filter clean,$(MAKECMDGOALS)),)
+	$(shell rm -rf $(BUILD_DIR))
+endif

riscv-sbi/core/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile for Phoenix SBI
+#
+# Copyright 2024 Phoenix Systems
+#
+# %LICENSE%
+#
+
+include platform/$(TARGET_SUBFAMILY)/Makefile
+include core/extensions/Makefile
+include core/fdt/Makefile
+
+OBJS += $(addprefix $(PREFIX_O)core/, _interrupts.o _start.o _string.o csr.o exceptions.o hart.o interrupts.o sbi.o string.o)

riscv-sbi/core/_interrupts.S

@@ -0,0 +1,178 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Phoenix SBI
+ *
+ * Interrupt stubs
+ *
+ * Copyright 2023, 2024 Phoenix Systems
+ * Author: Lukasz Leczkowski
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+#define __ASSEMBLY__
+
+
+#include "csr.h"
+
+.text
+
+.align 2
+
+.global _interrupts_dispatch
+.type _interrupts_dispatch, @function
+_interrupts_dispatch:
+	csrrw a1, CSR_MSCRATCH, a1  /* a1 = &perHartData[hartid] */
+	sd a0, 8(a1)                /* Save a0 */
+
+	csrr a0, CSR_MSTATUS
+
+	/* Determine in which mode we were executing before interrupt
+	 * MPP = 3 -> machine mode
+	 */
+	srli a0, a0, 11
+	xori a0, a0, 3
+	bnez a0, 1f
+
+	/* Machine mode */
+	sd sp, -272(sp)
+
+	addi sp, sp, -280
+	j 2f
+
+1:
+	/* U/S mode
+	 * Load machine stack pointer from hart data
+	 */
+	ld a0, (a1)
+
+	/* Save task's stack pointer */
+	sd sp, -272(a0)
+
+	/* Swap to machine stack */
+	addi sp, a0, -280
+
+2:
+	/* restore a0, a1 */
+	ld a0, 8(a1)
+	csrrw a1, CSR_MSCRATCH, a1
+
+	/* Save context */
+	sd ra, (sp)
+	sd gp, 16(sp)
+	sd tp, 24(sp)
+	sd t0, 32(sp)
+	sd t1, 40(sp)
+	sd t2, 48(sp)
+	sd s0, 56(sp)
+	sd s1, 64(sp)
+	sd a0, 72(sp)
+	sd a1, 80(sp)
+	sd a2, 88(sp)
+	sd a3, 96(sp)
+	sd a4, 104(sp)
+	sd a5, 112(sp)
+	sd a6, 120(sp)
+	sd a7, 128(sp)
+	sd s2, 136(sp)
+	sd s3, 144(sp)
+	sd s4, 152(sp)
+	sd s5, 160(sp)
+	sd s6, 168(sp)
+	sd s7, 176(sp)
+	sd s8, 184(sp)
+	sd s9, 192(sp)
+	sd s10, 200(sp)
+	sd s11, 208(sp)
+	sd t3, 216(sp)
+	sd t4, 224(sp)
+	sd t5, 232(sp)
+	sd t6, 240(sp)
+
+	csrr s0, CSR_MSTATUS
+	csrr s1, CSR_MEPC
+	csrr s2, CSR_MCAUSE
+
+	sd s0, 248(sp)   /* mstatus */
+	sd s1, 256(sp)   /* mepc */
+	sd s2, 264(sp)   /* mcause */
+
+	/* Check interrupt source */
+	li t0, MCAUSE_INTR
+	and t1, s2, t0
+	andi s0, s2, MCAUSE_IRQ_MSK /* Exception code */
+	beqz t1, _interrupts_notIrq
+
+_interrupts_dispatchIntr:
+	mv a0, s0
+	call interrupts_dispatch
+	tail _interrupts_restoreAll
+
+_interrupts_notIrq:
+	li s2, MCAUSE_S_ECALL
+	bne s0, s2, _interrupts_dispatchExc
+
+	/* s1 = mepc, move past ecall instruction */
+	addi s1, s1, 4
+	sd s1, 256(sp)
+
+	/* a0-a7 are preserved */
+	call sbi_dispatchEcall
+	tail _interrupts_restoreAfterEcall
+
+_interrupts_dispatchExc:
+	csrr s1, CSR_MTVAL
+	sd s1, 272(sp)   /* mtval */
+
+	mv a0, s0
+	mv a1, sp
+	call exceptions_dispatch
+
+_interrupts_restoreAll:
+	ld a0, 72(sp)
+	ld a1, 80(sp)
+
+_interrupts_restoreAfterEcall:
+	ld s0, 248(sp)
+	csrw CSR_MSTATUS, s0
+
+	ld s0, 256(sp)
+	csrw CSR_MEPC, s0
+
+	ld ra, (sp)
+	ld gp, 16(sp)
+	ld tp, 24(sp)
+	ld t0, 32(sp)
+	ld t1, 40(sp)
+	ld t2, 48(sp)
+	ld s0, 56(sp)
+	ld s1, 64(sp)
+	ld a2, 88(sp)
+	ld a3, 96(sp)
+	ld a4, 104(sp)
+	ld a5, 112(sp)
+	ld a6, 120(sp)
+	ld a7, 128(sp)
+	ld s2, 136(sp)
+	ld s3, 144(sp)
+	ld s4, 152(sp)
+	ld s5, 160(sp)
+	ld s6, 168(sp)
+	ld s7, 176(sp)
+	ld s8, 184(sp)
+	ld s9, 192(sp)
+	ld s10, 200(sp)
+	ld s11, 208(sp)
+	ld t3, 216(sp)
+	ld t4, 224(sp)
+	ld t5, 232(sp)
+	ld t6, 240(sp)
+
+	/* Restore task's stack pointer */
+	ld sp, 8(sp)
+
+	mret
+.size _interrupts_dispatch, .-_interrupts_dispatch