rtt: Reserve memory for RTT buffers in memory map

JIRA: RTOS-754

devices/pipe-rtt/rtt.c

@@ -55,8 +55,9 @@ struct rtt_desc {
 
 static struct {
 	/* NOTE: each buffer must be aligned to cache line */
-	unsigned char bytes[1024] __attribute__((aligned(32)));
-} rttBufferPool[RTT_TXCHANNELS + RTT_RXCHANNELS];
+	unsigned char tx[RTT_TXCHANNELS][1024] __attribute__((aligned(32)));
+	unsigned char rx[RTT_RXCHANNELS][1024] __attribute__((aligned(32)));
+} rttBuffers __attribute__((section(".rttmem")));
 
 
 static const char rtt_tagBackward[] = RTT_TAG_BACKWARD;
@@ -171,19 +172,20 @@ void rtt_init(void *addr)
 	rtt->txChannels = RTT_TXCHANNELS;
 	rtt->rxChannels = RTT_RXCHANNELS;
 
-	m = 0;
 	for (n = 0; n < rtt->txChannels; n++) {
 		rtt->txChannel[n].name = rtt_txName[n];
-		rtt->txChannel[n].ptr = rttBufferPool[m].bytes;
-		rtt->txChannel[n].sz = sizeof(rttBufferPool[m].bytes);
-		m++;
+		rtt->txChannel[n].ptr = rttBuffers.tx[n];
+		rtt->txChannel[n].sz = sizeof(rttBuffers.tx[n]);
+		rtt->txChannel[n].wr = 0;
+		rtt->txChannel[n].rd = 0;
 	}
 
 	for (n = 0; n < rtt->rxChannels; n++) {
 		rtt->rxChannel[n].name = rtt_rxName[n];
-		rtt->rxChannel[n].ptr = rttBufferPool[m].bytes;
-		rtt->rxChannel[n].sz = sizeof(rttBufferPool[m].bytes);
-		m++;
+		rtt->rxChannel[n].ptr = rttBuffers.rx[n];
+		rtt->rxChannel[n].sz = sizeof(rttBuffers.rx[n]);
+		rtt->rxChannel[n].wr = 0;
+		rtt->rxChannel[n].rd = 0;
 	}
 
 	n = 0;

hal/armv7m/imxrt/10xx/105x/Makefile

@@ -15,7 +15,7 @@ CFLAGS+= -mfloat-abi=soft
 PLO_COMMANDS ?= alias app blob bridge call console copy devices dump echo erase go help kernel \
   kernelimg map mem mpu otp phfs ptable reboot script stop wait
 
-# pipe-rtt is disabled due to small amount of space in DTCM; RTT_ADDR is not defined for this architecture
+# pipe-rtt is disabled due to small amount of space in DTCM; RTT_ENABLED is not defined for this architecture
 PLO_ALLDEVICES := usbc-cdc uart-imxrt106x flash-imxrt
 
 OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/imxrt/10xx/105x/, _init.o imxrt.o)

hal/armv7m/imxrt/10xx/106x/peripherals.h

@@ -26,9 +26,8 @@
 
 
 /* DEBUG - RTT PIPE */
-#ifndef RTT_ADDR
-/* RTT descriptors location, last 256 bytes of DTCM */
-#define RTT_ADDR (0x20058000 - 0x100)
+#ifndef RTT_ENABLED
+#define RTT_ENABLED 1
 #endif
 
 

hal/armv7m/imxrt/117x/peripherals.h

@@ -27,9 +27,8 @@
 
 /* DEBUG - RTT PIPE */
 
-#ifndef RTT_ADDR
-/* RTT descriptors location, last 256 bytes of DTCM */
-#define RTT_ADDR (0x20040000 - 0x100)
+#ifndef RTT_ENABLED
+#define RTT_ENABLED 1
 #endif
 
 

hal/armv7m/imxrt/hal.c

@@ -30,6 +30,9 @@ extern char __data_start[], __data_end[];
 extern char __bss_start[], __bss_end[];
 extern char __heap_base[], __heap_limit[];
 extern char __stack_top[], __stack_limit[];
+#if RTT_ENABLED == 1
+extern char __rttmem_rttcb[];
+#endif
 
 /* Timer */
 extern void timer_init(void);
@@ -58,8 +61,8 @@ void hal_init(void)
 	timer_init();
 	otp_init();
 
-#ifdef RTT_ADDR
-	rtt_init((void *)RTT_ADDR);
+#if RTT_ENABLED == 1
+	rtt_init(__rttmem_rttcb);
 #endif
 
 	console_init();

hal/armv7m/stm32/hal.c

@@ -33,6 +33,9 @@ extern char __data_start[], __data_end[];
 extern char __bss_start[], __bss_end[];
 extern char __heap_base[], __heap_limit[];
 extern char __stack_top[], __stack_limit[];
+#if RTT_ENABLED == 1
+extern char __rttmem_rttcb[];
+#endif
 
 /* Timer */
 extern void timer_init(void);
@@ -60,8 +63,8 @@ void hal_init(void)
 	mpu_init();
 	timer_init();
 
-#ifdef RTT_ADDR
-	rtt_init((void *)RTT_ADDR);
+#if RTT_ENABLED == 1
+	rtt_init(__rttmem_rttcb);
 #endif
 
 	console_init();

ld/armv7m4-stm32l4x6.ldt

@@ -33,13 +33,17 @@
 /* Space reserved for kernel data */
 #define AREA_KERNEL 0x10000
 
+/* Space reserved for RTT control block and buffers */
+#define SIZE_RTTMEM (2 * 2 * 0x400 + 256)
+
 
 #if defined(__LINKER__)
 
 /* Memory map setup */
 MEMORY
 {
-	m_sram    (rwx) : ORIGIN = RAM_ADDR + AREA_KERNEL, LENGTH = (256k + 64k) - AREA_KERNEL
+	m_sram    (rwx) : ORIGIN = RAM_ADDR + AREA_KERNEL, LENGTH = (256k + 64k) - AREA_KERNEL - SIZE_RTTMEM
+	m_rttmem  (rw)  : ORIGIN = RAM_ADDR + (256k + 64k) - SIZE_RTTMEM, LENGTH = SIZE_RTTMEM
 	m_flash2  (rx)  : ORIGIN = FLASH_PROGRAM_2_ADDR, LENGTH = 512k
 	m_flash1  (rx)  : ORIGIN = FLASH_PROGRAM_1_ADDR, LENGTH = 512k
 }
@@ -51,8 +55,10 @@ REGION_ALIAS("DATA", m_sram);
 REGION_ALIAS("BSS", m_sram);
 REGION_ALIAS("HEAP", m_sram);
 REGION_ALIAS("STACK", m_sram);
+REGION_ALIAS("RTTMEM", m_rttmem);
 
 #include "common/plo-arm.lds"
+#include "common/plo-rtt.lds"
 
 #endif /* end of __LINKER__ */
 

ld/armv7m7-imxrt106x.ldt

@@ -26,6 +26,9 @@
 /* Space reserved for kernel data */
 #define AREA_KERNEL 0x2000
 
+/* Space reserved for RTT control block and buffers */
+#define SIZE_RTTMEM (2 * 2 * 0x400 + 256)
+
 
 #if defined(__LINKER__)
 
@@ -51,7 +54,8 @@ MEMORY
 	/* TODO: use FLEXRAM_CONFIG value to setup ocram/itcm/dtcm partitioning (*32k) */
 	m_itcm    (rwx) : ORIGIN = 0x00000000, LENGTH = FLEXRAM_ITCM_AREA
 	m_itext   (rwx) : ORIGIN = FLEXRAM_ITEXT_ADDR, LENGTH = FLEXRAM_ITEXT_AREA
-	m_dtcm    (rw)  : ORIGIN = 0x20000000 + AREA_KERNEL, LENGTH = FLEXRAM_DTCM_AREA - AREA_KERNEL
+	m_dtcm    (rw)  : ORIGIN = 0x20000000 + AREA_KERNEL, LENGTH = FLEXRAM_DTCM_AREA - AREA_KERNEL - SIZE_RTTMEM
+	m_rttmem  (rw)  : ORIGIN = 0x20000000 + FLEXRAM_DTCM_AREA - SIZE_RTTMEM, LENGTH = SIZE_RTTMEM
 	m_ocram   (rwx) : ORIGIN = 0x20200000, LENGTH = 0 * 32k
 	m_flash   (rx)  : ORIGIN = 0x70000000, LENGTH = 128k /* Not actual flash size. Initial flash size to be put into FCB block for imxrt BootROM init procedure only */
 }
@@ -78,8 +82,10 @@ REGION_ALIAS("TCM_TEXT", m_itext);
 REGION_ALIAS("BSS", m_dtcm);
 REGION_ALIAS("HEAP", m_dtcm);
 REGION_ALIAS("STACK", m_dtcm);
+REGION_ALIAS("RTTMEM", m_rttmem);
 
 #include "common/plo-arm.lds"
+#include "common/plo-rtt.lds"
 
 #endif /* end of __LINKER__ */
 

ld/armv7m7-imxrt117x.ldt

@@ -29,6 +29,9 @@
 /* Space reserved for bootloader */
 #define AREA_BOOTLOADER 0x10000
 
+/* Space reserved for RTT control block and buffers */
+#define SIZE_RTTMEM (2 * 2 * 0x400 + 256)
+
 
 #if defined(__LINKER__)
 
@@ -53,7 +56,8 @@ MEMORY
 {
 	m_itcm    (rwx) : ORIGIN = 0x00000000, LENGTH = FLEXRAM_ITCM_AREA
 	m_itext   (rwx) : ORIGIN = 0x00000000 + FLEXRAM_ITEXT_ADDR, LENGTH = FLEXRAM_ITEXT_AREA
-	m_dtcm    (rw)  : ORIGIN = 0x20000000 + AREA_KERNEL, LENGTH = FLEXRAM_DTCM_AREA - AREA_KERNEL
+	m_dtcm    (rw)  : ORIGIN = 0x20000000 + AREA_KERNEL, LENGTH = FLEXRAM_DTCM_AREA - AREA_KERNEL - SIZE_RTTMEM
+	m_rttmem  (rw)  : ORIGIN = 0x20000000 + FLEXRAM_DTCM_AREA - SIZE_RTTMEM, LENGTH = SIZE_RTTMEM
 	m_ocram1  (rwx) : ORIGIN = 0x20240000 + AREA_BOOTLOADER, LENGTH = (8 * 32k) - AREA_BOOTLOADER
 	m_ocram2  (rwx) : ORIGIN = 0x202c0000, LENGTH = 512k
 	m_flash   (rx)  : ORIGIN = 0x30000000, LENGTH = 128k /* Not actual flash size. Initial flash size to be put into FCB block for imxrt BootROM init procedure only */
@@ -81,8 +85,10 @@ REGION_ALIAS("TCM_TEXT", m_itext);
 REGION_ALIAS("BSS", m_dtcm);
 REGION_ALIAS("HEAP", m_dtcm);
 REGION_ALIAS("STACK", m_dtcm);
+REGION_ALIAS("RTTMEM", m_rttmem);
 
 #include "common/plo-arm.lds"
+#include "common/plo-rtt.lds"
 
 #endif /* end of __LINKER__ */
 

ld/common/plo-rtt.lds

@@ -0,0 +1,12 @@
+/* Section for RTT control block and buffers */
+SECTIONS
+{
+    .rttmem ORIGIN(RTTMEM) (NOLOAD):
+	{
+		KEEP(*(.rttmem))
+		. = ABSOLUTE(ORIGIN(RTTMEM) + LENGTH(RTTMEM) - 256);
+		__rttmem_rttcb = .;
+		. = ALIGN(4);
+	} > RTTMEM
+
+}