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imxrt-flash: fast read fix for ISSI NOR flash #335

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merged 1 commit into from
Jun 25, 2024

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ziemleszcz
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ISSI NOR chips use selecteble dummy cycles to support fast read command. For 133 MHz fast read should include 11 dummy cycles (default is 6). To set correct number of dummy cycles:

  • FCFB and flexspi_init() use 60 MHz clock and normal read
  • add custom ISSI commands and nor_issiInit()
  • add flexspi_postinit() which switches to final 133 MHz clock

DONE: RTOS-128

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Motivation and Context

Types of changes

  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)
  • Chore (refactoring, style fixes, git/CI config, submodule management, no code logic changes)

How Has This Been Tested?

  • Already covered by automatic testing.
  • New test added: (add PR link here).
  • Tested by hand on: (imxrt1170).

Checklist:

  • My change requires a change to the documentation.
  • I have updated the documentation accordingly.
  • I have added tests to cover my changes.
  • All new and existing linter checks and tests passed.
  • My changes generate no new compilation warnings for any of the targets.

Special treatment

  • This PR needs additional PRs to work (list the PRs, preferably in merge-order).
  • I will merge this PR by myself when appropriate.

@agkaminski
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@ziemleszcz increase here:

FLEXRAM_ITEXT_AREA = 14 * SIZE_PAGE;

It can be done consequence free (until kernel still fits in the itcm it is :))

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github-actions bot commented Jun 25, 2024

Unit Test Results

7 460 tests   6 745 ✅  37m 46s ⏱️
  420 suites    715 💤
    1 files        0 ❌

Results for commit 036e0ae.

♻️ This comment has been updated with latest results.

@ziemleszcz ziemleszcz marked this pull request as ready for review June 25, 2024 14:09
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LGTM

ISSI NOR chips use selecteble dummy cycles to support fast read command.
For 133 MHz fast read should include 11 dummy cycles (default is 6). To
set correct number of dummy cycles:

 - FCFB and flexspi_init() use 60 MHz clock and normal read
 - add custom ISSI commands and nor_issiInit()
 - add flexspi_postinit() which switches to final 133 MHz clock

DONE: RTOS-128
@agkaminski agkaminski merged commit 9bdcdeb into master Jun 25, 2024
32 checks passed
@agkaminski agkaminski deleted the ziemleszcz/RTOS-128 branch June 25, 2024 17:21
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3 participants