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Modify vset*vl* insts behaviors [Work in progress] #21

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@hnpl hnpl commented Nov 12, 2022

This patch removes stalls when vsetvl insts not executed.

At decode time, a decoded vector inst will get the identical vtype and vl values of the previous vector inst. This is accomplished by ,

  • Adding vtype and vl to PCState.
  • At the decode time, the next instruction will get its pcstate from the previously decoded instruction. Thus they will share the identical vtype and vl values.
  • The vsetvl instructions are marked as control instructions. Upon their execution time, the vtype and vl values will be updated accordingly. Like a branch instruction, if there's a mismatch between the old and the new values of vtype and vl, the pipeline will be flushed. Afterwards, since the vtype and vl in pcstate of the vsetvl instruction is updated, the followed decoded instructions will receive an updated vtype and vl.

I ran some small tests and it seems that, currently, this patch works for AtomicSimpleCPU and TimingSimpleCPU. I haven't test this with MinorCPU.
I haven't looked at how vector memory instructions are microcoded, so I'll look into that to figure out the problem with O3CPU.

Note: this change has a commit removing the github workflow as github doesn't allow me to push if the workflow exists. Please remove this commit prior to merging.

hnpl added 8 commits October 26, 2022 21:54
Signed-off-by: Hoa Nguyen <[email protected]>
Change-Id: I741aed8b982adab58523564f28aedcc0f970eaa3
Signed-off-by: Hoa Nguyen <[email protected]>
Change-Id: If8765b27674be86d444fc6d275484e3f94c20282
Signed-off-by: Hoa Nguyen <[email protected]>
Per RVV spec 1.0, VLMAX = 2**16

Change-Id: I27d93ac602ca750648348419fe7923f459f18191
Signed-off-by: Hoa Nguyen <[email protected]>
Change-Id: I23d0c0629c71e432e89dcb330e043fc638ca6905
Signed-off-by: Hoa Nguyen <[email protected]>
- The vsetvl* insts, apart from the spec, also update the vl and
vtype stored in the next pc PCState.
- The vsetvl* insts are marked as control instructions and behave
like a branch instruction. Upon the execution stage, the values of
vl and vtype will be updated, and the updated values will be
compared to the initial values. If they are different, the
pipeline will be flushed. The next instruction will get the PCState
from this instruction, so it will have the updated vl and vtype.

Change-Id: I8d988fd8ca833021908694bd1713cb3963bdfa3c
Signed-off-by: Hoa Nguyen <[email protected]>
Change-Id: I8d8101fb3522beaa22cb928ef3458dfaa3d86271
Signed-off-by: Hoa Nguyen <[email protected]>
Change-Id: I14172a4cf517f3f81d9cf3928c7db32f49644b20
Signed-off-by: Hoa Nguyen <[email protected]>
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