GitHub - plessl/zippy: Cycle accurate co-simulation model of a reconfigurable CPU

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Latest commit plessl Updated license Apr 6, 2010 f3ecb05 · Apr 6, 2010 History 8 Commits
app	app	[CHANGED] Forgotten commit in working copy	Jul 15, 2007
cosim	cosim	[NEW] Initial import into repository at code.google.com	Jul 15, 2007
doc	doc	[NEW] Initial import into repository at code.google.com	Jul 15, 2007
public_html	public_html	[NEW] Initial import into repository at code.google.com	Jul 15, 2007
simple	simple	[CHANGED] Added missing files from SimpleScalar distribution.	Jul 15, 2007
vhdl	vhdl	[NEW] Initial import into repository at code.google.com	Jul 15, 2007
ztools	ztools	Remove .DS_Store files.	Nov 30, 2009
.gitignore	.gitignore	Add .gitignore file	Nov 30, 2009
AUTHORS	AUTHORS	[NEW] Initial import into repository at code.google.com	Jul 15, 2007
LICENSE	LICENSE	Updated license	Apr 6, 2010
Makefile	Makefile	[NEW] Initial import into repository at code.google.com	Jul 15, 2007
README	README	Add README.	Oct 23, 2009
TODO	TODO	[NEW] Initial import into repository at code.google.com	Jul 15, 2007
make.defs	make.defs	[NEW] Initial import into repository at code.google.com	Jul 15, 2007

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Zippy is a detailed simulation model for a reconfigurable CPU architecture that has been developed in the Zippy Research Project at ETH Zurich.

Zippy consists of a CPU that is interfaced to a coarse-grained, dynamically reconfigurable array. The CPU is simulated with the SimpleScalar CPU simulator, the reconfigurable array is specified as cycle accurate VHDL model. These models are integrated with a co-simulation environment into a cycle-accurate, system-level co-simulation framework.