GitHub - plessl/zippy: Cycle accurate co-simulation model of a reconfigurable CPU

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Cycle accurate co-simulation model of a reconfigurable CPU

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Name		Name	Last commit message	Last commit date
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app		app
cosim		cosim
doc		doc
public_html		public_html
simple		simple
vhdl		vhdl
ztools		ztools
.gitignore		.gitignore
AUTHORS		AUTHORS
LICENSE		LICENSE
Makefile		Makefile
README		README
TODO		TODO
make.defs		make.defs

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Zippy is a detailed simulation model for a reconfigurable CPU architecture that has been developed in the Zippy Research Project at ETH Zurich.

Zippy consists of a CPU that is interfaced to a coarse-grained, dynamically reconfigurable array. The CPU is simulated with the SimpleScalar CPU simulator, the reconfigurable array is specified as cycle accurate VHDL model. These models are integrated with a co-simulation environment into a cycle-accurate, system-level co-simulation framework.