ch4/posix: making topology aware SHM default to enabled

Fix the performance degradation on Intel Sapphire Rapids after
introducing topo-aware SHM. This problem only happens when building
with Intel compiler. The problem was topo-aware default
to disabled. It uses regular memcpy for inter-NUMA message which
is different from v4.2.2 (uses non-temporal copy).

The reason this is disabled by default was due to using non-temporal
copy results in higher latency in small message. After more testing
with different CPUs (broadwell, skylake, cascade, icelake, milan),
It seems only skylake, cascade and icelake has this issue on small
message. It is probably OK to make topo-aware SHM default to enabled.

src/mpid/ch4/shm/posix/posix_init.c

@@ -40,7 +40,7 @@
     - name        : MPIR_CVAR_CH4_SHM_POSIX_TOPO_ENABLE
       category    : CH4
       type        : boolean
-      default     : false
+      default     : true
       class       : none
       verbosity   : MPI_T_VERBOSITY_USER_BASIC
       scope       : MPI_T_SCOPE_ALL_EQ